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if diversity receiver ad6655 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features snr = 74.5 dbc (75.5 dbfs) in a 32.7 mhz bw at 70 mhz @ 150 msps sfdr = 80 dbc to 70 mhz @ 150 msps 1.8 v analog supply operation 1.8 v to 3.3 v cmos output supply or 1.8 v lvds output supply integer 1-to-8 input clock divider integrated dual-channel adc sample rates up to 150 msps if sampling frequencies to 450 mhz internal adc voltage reference integrated adc sample-and-hold inputs flexible analog input range: 1 v p-p to 2 v p-p adc clock duty cycle stabilizer 95 db channel isolation/crosstalk integrated wideband digital downconverter (ddc) 32-bit complex, numerically controlled oscillator (nco) decimating half-band filter and fir filter supports real and complex output modes fast attack/threshold detect bits composite signal monitor energy-saving power-down modes applications communications diversity radio systems multimode digital receivers (3g) td-scdma, wimax, wcdma, cdma2000, gsm, edge, lte i/q demodulation systems smart antenna systems general-purpose software radios broadband data applications product highlights 1. integrated dual, 14-bit, 150 msps adc. 2. integrated wideband decimation filter and 32-bit complex nco. 3. fast overrange detect and signal monitor with serial output. 4. proprietary differential input maintains excellent snr performance for input frequencies up to 450 mhz. 5. flexible output modes, including independent cmos, interleaved cmos, iq mode cmos, and interleaved lvds. 6. sync input allows synchronization of multiple devices. 7. 3-bit spi port for register programming and register readback. functional block diagram 06709-001 avdd fd[0:3] a dvdd drvdd ad6655 vin+a vin?a vref s ense cml rbias sha sync fd[0:3]b smi sdfs smi sclk/ pdwn smi sdo/ oeb ref select adc i q q i vin?b vin+b d13a d0a clk+ clk? dcoa dcob d13b d0b sha adc multi-chip sync signal monitor divide 1 to 8 duty cycle stabilizer agnd signal monitor interface cmos/lvds output buffer signal monitor data sdio/ dcs sclk/ dfs csb drgnd spi programming data fd bits/threshold detect fd bits/threshold detect 32-bit tuning nco f adc /8 nco lp/hp decimating hb filter + fir lp/hp decimating hb filter + fir cmos output buffer dco generation notes 1. pin names are for the cmos pin configuration only; see figure 10 for lvds pin names. figure 1.
ad6655 rev. 0 | page 2 of 84 table of contents features .............................................................................................. 1 applications....................................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications..................................................................................... 5 adc dc specificationsad6655bcpz-80/ ad6655bcpz-105 ......................................................................... 5 adc dc specificationsad6655bcpz-125/ ad6655bcpz-150 ......................................................................... 6 adc ac specificationsad6655bcpz-80/ ad6655bcpz-105 ......................................................................... 7 adc ac specificationsad6655bcpz-125/ ad6655bcpz-150 ......................................................................... 8 digital specificationsad6655bcpz-80/ ad6655bcpz-105 ......................................................................... 9 digital specificationsad6655bcpz-125/ ad6655bcpz-150 ....................................................................... 11 switching specificationsad6655bcpz-80/ ad6655bcpz-105 ....................................................................... 13 switching specificationsad6655bcpz-125/ ad6655bcpz-150 ....................................................................... 14 timing specifications ................................................................ 15 absolute maximum ratings.......................................................... 18 thermal characteristics ............................................................ 18 esd caution................................................................................ 18 pin configurations and function descriptions ......................... 19 equivalent circuits ......................................................................... 23 typical performance characteristics ........................................... 24 theory of operation ...................................................................... 29 adc architecture ...................................................................... 29 analog input considerations.................................................... 29 voltage reference ....................................................................... 31 clock input considerations ...................................................... 32 power dissipation and standby mode..................................... 34 digital outputs ........................................................................... 35 digital downconverter .................................................................. 37 downconverter modes .............................................................. 37 numerically controlled oscillator (nco) ............................. 37 half-band decimating filter and fir filter........................... 37 f adc /8 fixed-frequency nco ................................................... 37 numerically controlled oscillator (nco) ................................. 38 frequency translation ............................................................... 38 nco synchronization ............................................................... 38 phase offset................................................................................. 38 nco amplitude and phase dither.......................................... 38 decimating half-band filter and fir filter................................ 39 half-band filter coefficients.................................................... 39 half-band filter features .......................................................... 39 fixed-coefficient fir filter...................................................... 39 synchronization.......................................................................... 40 combined filter performance.................................................. 40 final nco ................................................................................... 40 adc overrange and gain control.............................................. 41 fast detect overview................................................................. 41 adc fast magnitude ................................................................. 41 adc overrange (or)................................................................ 42 gain switching............................................................................ 42 signal monitor ................................................................................ 44 peak detector mode................................................................... 44 rms/ms magnitude mode....................................................... 44 threshold crossing mode......................................................... 45 additional control bits ............................................................. 45 dc correction ............................................................................ 45 signal monitor sport output ................................................ 46 channel/chip synchronization.................................................... 47 serial port interface (spi).............................................................. 48 configuration using the spi..................................................... 48 hardware interface..................................................................... 48 configuration without the spi ................................................ 49 spi accessible features.............................................................. 49 memory map .................................................................................. 50 reading the memory map register table............................... 50 memory map register table..................................................... 51 memory map register description ......................................... 55 applications information .............................................................. 59 design guidelines ...................................................................... 59 evaluation board ............................................................................ 61 power supplies ............................................................................ 61
ad6655 rev. 0 | page 3 of 84 input signals ................................................................................61 output signals .............................................................................61 default operation and jumper selection settings..................62 alternative clock configurations.............................................62 alternative analog input drive configuration ......................63 schematics....................................................................................64 evaluation board layouts ..........................................................74 bill of materials ...........................................................................82 outline dimensions........................................................................84 ordering guide ...........................................................................84 revision history 11/07revision 0: initial version
ad6655 rev. 0 | page 4 of 84 general description the ad6655 is a mixed-signal intermediate frequency (if) receiver consisting of dual 14-bit, 80 msps/105 msps/125 msps/150 msps adcs and a wideband digital downconverter (ddc). the ad6655 is designed to support communications applications where low cost, small size, and versatility are desired. the dual adc core features a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. an integrated voltage reference eases design consid- erations. a duty cycle stabilizer is provided to compensate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. adc data outputs are internally connected directly to the digital downconverter (ddc) of the receiver, simplifying layout and reducing interconnection parasitics. the digital receiver has two channels and provides processing flexibility. each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically contro lled oscillator (nco)), a half- band decimating filter, a fixed fir filter, and an f adc /8 fixed- frequency nco. in addition to the receiver ddc, the ad6655 has several functions that simplify the automatic gain control (agc) function in the system receiver. the fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency. in addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the adc with low latency. if the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition. the second agc-related function is the signal monitor. this block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. after digital processing, data can be routed directly to the two external 14-bit output ports. these outputs can be set from 1.8 v to 3.3 v cmos or as 1.8 v lvds. the cmos data can also be output in an interleaved configuration at a double data rate using only port a. the ad6655 receiver digitizes a wide spectrum of if frequencies. each receiver is designed for simultaneous reception of the main channel and the diversity channel. this if sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. flexible power-down options allow significant power savings, when desired. programming for setup and control is accomplished using a 3-bit spi-compatible serial interface. the ad6655 is available in a 64-lead lfcsp and is specified over the industrial temperature range of ?40c to +85c.
ad6655 rev. 0 | page 5 of 84 specifications adc dc specificationsad6655bcpz-80/ad6655bcpz-105 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 1. ad6655bcpz-80 ad6655bcpz-105 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full 0.2 0.6 0.2 0.6 % fsr gain error full ?3.6 ?1.8 ?0.1 ?4.3 ?2.2 ?0.5 % fsr matching characteristic offset error 25c 0.2 0.6 0.2 0.6 % fsr gain error 25c 0.2 0.75 0.2 0.75 % fsr temperature drift offset error full 15 15 ppm/c gain error full 95 95 ppm/c internal voltage reference output voltage error (1 v mode) full 5 18 5 18 mv load regulation @ 1.0 ma full 7 7 mv input-referred noise vref = 1.0 v 25c 0.85 0.85 lsb rms analog input input span, vref = 1.0 v full 2 2 v p-p input capacitance 1 full 8 8 pf vref input resistance full 6 6 k power supplies supply voltage avdd, dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd (cmos mode) full 1.7 3.3 3.6 1.7 3.3 3.6 v drvdd (lvds mode) full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd 2 , 3 full 235 315 ma i dvdd 2 , 3 full 175 420 225 575 ma i drvdd 2 (3.3 v cmos) full 18 21 ma i drvdd 2 (1.8 v cmos) full 8 11 ma i drvdd 2 (1.8 v lvds) full 55 56 ma power consumption dc input full 470 490 620 650 mw sine wave input 2 (drvdd = 1.8 v) full 755 995 mw sine wave input 2 (drvdd = 3.3 v) full 800 1040 mw standby power 4 full 52 68 mw power-down power full 2.5 8 2.5 8 mw 1 input capacitance refers to the effective capacitance between one differential input pin and agnd. see figure 11 for the equiv alent analog input structure. 2 measured with a 9.7 mhz, full-scale sine wave input, nco enabled with a frequency of 13 mhz, fir filter enabled and the f s /8 output mix enabled with approximately 5 pf loading on each output bit. 3 the maximum limit applies to the combination of i avdd and i dvdd currents. 4 standby power is measured with a dc input and with the clk pin inactive (set to avdd or agnd).
ad6655 rev. 0 | page 6 of 84 adc dc specificationsad6655bcpz-125/ad6655bcpz-150 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 2. ad6655bcpz-125 ad6655bcpz-150 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full 0.3 0.6 0.2 0.6 % fsr gain error full ?4.7 ?2.7 ?0.8 ?5.1 ?3.2 ?1.0 % fsr matching characteristic offset error 25c 0.3 0.7 0.2 0.7 % fsr gain error 25c 0.1 0.7 0.2 0.8 % fsr temperature drift offset error full 15 15 ppm/c gain error full 95 95 ppm/c internal voltage reference output voltage error (1 v mode) full 5 18 5 18 mv load regulation @ 1.0 ma full 7 7 mv input-referred noise vref = 1.0 v 25c 0.85 0.85 lsb rms analog input input span, vref = 1.0 v full 2 2 v p-p input capacitance 1 full 8 8 pf vref input resistance full 6 6 k power supplies supply voltage avdd, dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd (cmos mode) full 1.7 1.8 3.6 1.7 1.8 3.6 v drvdd (lvds mode) full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd 2 , 3 full 390 440 ma i dvdd 2 , 3 full 270 705 320 805 ma i drvdd 2 (3.3 v cmos) full 26 28 ma i drvdd 2 (1.8 v cmos) full 13 17 ma i drvdd 2 (1.8 v lvds) full 57 57 ma power consumption dc input full 770 810 870 920 mw sine wave input 2 (drvdd = 1.8 v) full 1215 1395 mw sine wave input 2 (drvdd = 3.3 v) full 1275 1450 mw standby power 4 full 77 77 mw power-down power full 2.5 8 2.5 8 mw 1 input capacitance refers to the effective capacitance between one differential input pin and agnd. see figure 11 for the equiv alent analog input structure. 2 measured with a 9.7 mhz, full-scale sine wave input, nco enabled with a frequency of 13 mhz, fir filter enabled and the f s /8 output mix enabled with approximately 5 pf loading on each output bit. 3 the maximum limit applies to the combination of i avdd and i dvdd currents. 4 standby power is measured with a dc input, the clk pin inactive (set to avdd or agnd).
ad6655 rev. 0 | page 7 of 84 adc ac specificationsad6655bcpz-80/ad6655bcpz-105 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, nco enabled, half-band filter enabled, fir filter enabled, unless otherwise noted. table 3. ad6655bcpz-80 ad6655bcpz-105 parameter 1 temperature min typ max min typ max unit signal-to-noise-ratio (snr) f in = 2.4 mhz 25c 74.9 74.8 db f in = 70 mhz 25c 74.8 74.7 db full 73.0 73.0 db f in = 140 mhz 25c 74.5 74.3 db f in = 220 mhz 25c 73.4 73.4 db worst second or third harmonic f in = 2.4 mhz 25c ?86 ?86 dbc f in = 70 mhz 25c ?85 ?85 dbc full ?74 ?74 dbc f in = 140 mhz 25c ?84 ?84 dbc f in = 220 mhz 25c ?83 ?83 dbc spurious-free dynamic range (sfdr) f in = 2.4 mhz 25c 86 86 dbc f in = 70 mhz 25c 85 85 dbc full 74 74 dbc f in = 140 mhz 25c 84 84 dbc f in = 220 mhz 25c 83 83 dbc worst other harmonic or spur 2 f in = 2.4 mhz 25c ?93 ?93 dbc f in = 70 mhz 25c ?90 ?90 dbc full ?82 ?82 dbc f in = 140 mhz 25c ?89 ?89 dbc f in = 220 mhz 25c ?86 ?86 dbc two-tone sfdr f in = 29.12 mhz, 32.12 mhz (?7 dbfs) 25c 85 85 dbc f in = 169.12 mhz, 172.12 mhz (?7 dbfs) 25c 81 81 dbc crosstalk 3 full 95 95 db analog input bandwidth 25c 650 650 mhz 1 see application note an-835, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 see the applications infor mation section for more inform ation about the wors t other specificatio ns for the ad6655. 3 crosstalk is measured at 100 mhz with ?1 dbfs on on e channel and with no input on the alternate channel.
ad6655 rev. 0 | page 8 of 84 adc ac specificationsad6655bcpz-125/ad6655bcpz-150 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, nco enabled, half-band filter enabled, fir filter enabled, unless otherwise noted. table 4. ad6655bcpz-125 ad6655bcpz-150 parameter 1 temperature min typ max min typ max unit signal-to-noise-ratio (snr) f in = 2.4 mhz 25c 74.7 74.6 db f in = 70 mhz 25c 74.6 74.5 db full 73.0 72.5 db f in = 140 mhz 25c 74.2 73.9 db f in = 220 mhz 25c 73.3 73.0 db worst second or third harmonic f in = 2.4 mhz 25c ?86 ?85 dbc f in = 70 mhz 25c ?85 ?84 dbc full ?73 ?73 dbc f in = 140 mhz 25c ?84 ?83 dbc f in = 220 mhz 25c ?83 ?77 dbc spurious-free dynamic range (sfdr) f in = 2.4 mhz 25c 86 85 dbc f in = 70 mhz 25c 85 80 dbc full 73 73 dbc f in = 140 mhz 25c 84 76 dbc f in = 220 mhz 25c 83 74 dbc worst other harmonic or spur 2 f in = 2.4 mhz 25c ?92 ?87 dbc f in = 70 mhz 25c ?90 ?80 dbc full ?82 ?80 dbc f in = 140 mhz 25c ?88 ?76 dbc f in = 220 mhz 25c ?84 ?74 dbc two-tone sfdr f in = 29.12 mhz, 32.12 mhz (?7 dbfs) 25c 85 85 dbc f in = 169.12 mhz, 172.12 mhz (?7 dbfs) 25c 81 81 dbc crosstalk 3 full 95 95 db analog input bandwidth 25c 650 650 mhz 1 see application note an-835, understanding high speed adc testing and evaluation , for a complete set of definitions. 2 see the applications infor mation section for more inform ation about the wors t other specificatio ns for the ad6655. 3 crosstalk is measured at 100 mhz with ?1 dbfs on on e channel and with no input on the alternate channel.
ad6655 rev. 0 | page 9 of 84 digital specificationsad6655bcpz-80/ad6655bcpz-105 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ? 1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 5. ad6655bcpz-80 ad6655bcpz-105 parameter temp min typ max min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl internal common-mode bias full 1.2 1.2 v differential input voltage full 0.2 6 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 avdd 1.1 avdd v high level input voltage full 1.2 3.6 1.2 3.6 v low level input voltage full 0 0.8 0 0.8 v high level input current full ?10 +10 ?10 +10 a low level input current full ?10 +10 ?10 +10 a input capacitance full 4 4 pf input resistance full 8 10 12 8 10 12 k sync input logic compliance cmos cmos internal bias full 1.2 1.2 v input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v high level input voltage full 1.2 3.6 1.2 3.6 v low level input voltage full 0 0.8 0 0.8 v high level input current full ?10 +10 ?10 +10 a low level input current full ?10 +10 ?10 +10 a input capacitance full 4 4 pf input resistance full 8 10 12 8 10 12 k logic input (csb) 1 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?10 +10 ?10 +10 a low level input current full 40 132 40 132 a input resistance full 26 26 k input capacitance full 2 2 pf logic input (sclk/dfs) 2 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?92 ?135 ?92 ?135 a low level input current full ?10 +10 ?10 +10 a input resistance full 26 26 k input capacitance full 2 2 pf logic inputs (sdio/dcs, smi sdfs) 1 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?10 +10 ?10 +10 a low level input current full 38 128 38 128 a input resistance full 26 26 k input capacitance full 5 5 pf
ad6655 rev. 0 | page 10 of 84 ad6655bcpz-80 ad6655bcpz-105 parameter temp min typ max min typ max unit logic inputs (smi sdo/oeb, smi sclk/pdwn) 2 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?90 ?134 ?90 ?134 a low level input current full ?10 +10 ?10 +10 a input resistance full 26 26 k input capacitance full 5 5 pf digital outputs cmos modedrvdd = 3.3 v high level output voltage i oh = 50 a full 3.29 3.29 v i oh = 0.5 ma full 3.25 3.25 v low level output voltage i ol = 1.6 ma full 0.2 0.2 v i ol = 50 a full 0.05 0.05 v cmos modedrvdd = 1.8 v high level output voltage i oh = 50 a full 1.79 1.79 v i oh = 0.5 ma full 1.75 1.75 v low level output voltage i ol = 1.6 ma full 0.2 0.2 v i ol = 50 a full 0.05 0.05 v lvds mode, drvdd = 1.8 v differential output voltage (vod), ansi mode full 250 350 450 250 350 450 mv output offset voltage (vos), ansi mode full 1.15 1.25 1.35 1.15 1.25 1.35 v differential output voltage (vod), reduced swing mode full 150 200 280 150 200 280 mv output offset voltage (vos), reduced swing mode full 1.15 1.25 1.35 1.15 1.25 1.35 v 1 pull up. 2 pull down.
ad6655 rev. 0 | page 11 of 84 digital specificationsad6655bcpz-125/ad6655bcpz-150 avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, maximum sample rate, vin = ?1.0 dbfs differential input, 1.0 v internal reference, dcs enabled, unless otherwise noted. table 6. ad6655bcpz-125 ad6655bcpz-150 parameter temp min typ max min typ max unit differential clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl internal common-mode bias full 1.2 1.2 v differential input voltage full 0.2 6 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 v avdd 1.1 v avdd v high level input voltage full 1.2 3.6 1.2 3.6 v low level input voltage full 0 0.8 0 0.8 v high level input current full ?10 +10 ?10 +10 a low level input current full ?10 +10 ?10 +10 a input capacitance full 4 4 pf input resistance full 8 10 12 8 10 12 k sync input logic compliance cmos cmos internal bias full 1.2 1.2 v input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v high level input voltage full 1.2 3.6 1.2 3.6 v low level input voltage full 0 0.8 0 0.8 v high level input current full ?10 +10 ?10 +10 a low level input current full ?10 +10 ?10 +10 a input capacitance full 4 4 pf input resistance full 8 10 12 8 10 12 k logic input (csb) 1 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?10 +10 ?10 +10 a low level input current full 40 132 40 132 a input resistance full 26 26 k input capacitance full 2 2 pf logic input (sclk/dfs) 2 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?92 ?135 ?92 ?135 a low level input current full ?10 +10 ?10 +10 a input resistance full 26 26 k input capacitance full 2 2 pf logic inputs (sdio/dcs, smi sdfs) 1 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?10 +10 ?10 +10 a low level input current full 38 128 38 128 a input resistance full 26 26 k input capacitance full 5 5 pf
ad6655 rev. 0 | page 12 of 84 ad6655bcpz-125 ad6655bcpz-150 parameter temp min typ max min typ max unit logic inputs (smi sdo/oeb, smi sclk/pdwn) 2 high level input voltage full 1.22 3.6 1.22 3.6 v low level input voltage full 0 0.6 0 0.6 v high level input current full ?90 ?134 ?90 ?134 a low level input current full ?10 +10 ?10 +10 a input resistance full 26 26 k input capacitance full 5 5 pf digital outputs cmos modedrvdd = 3.3 v high level output voltage i oh = 50 a full 3.29 3.29 v i oh = 0.5 ma full 3.25 3.25 v low level output voltage i ol = 1.6 ma full 0.2 0.2 v i ol = 50 a full 0.05 0.05 v cmos modedrvdd = 1.8 v high level output voltage i oh = 50 a full 1.79 1.79 v i oh = 0.5 ma full 1.75 1.75 v low level output voltage i ol = 1.6 ma full 0.2 0.2 v i ol = 50 a full 0.05 0.05 v lvds modedrvdd = 1.8 v differential output voltage (vod), ansi mode full 250 350 450 250 350 450 mv output offset voltage (vos), ansi mode full 1.15 1.25 1.35 1.15 1.25 1.35 v differential output voltage (vod), reduced swing mode full 150 200 280 150 200 280 mv output offset voltage (vos), reduced swing mode full 1.15 1.25 1.35 1.15 1.25 1.35 v 1 pull up. 2 pull down.
ad6655 rev. 0 | page 13 of 84 switching specificationsad6655bcpz-80/ad6655bcpz-105 table 7. ad6655bcpz-80 ad6655bcpz-105 parameter temp min typ max min typ max unit clock input parameters input clock rate full 625 625 mhz conversion rate 1 dcs enabled full 20 80 20 105 msps dcs disabled full 10 80 10 105 msps clk perioddivide-by-1 mode (t clk ) full 12.5 9.5 ns clk pulse width high (t clkh ) divide-by-1 mode, dcs enabled full 3.75 6.25 8.75 2.85 4.75 6.65 ns divide-by-1 mode dcs disabled full 5.63 6.25 6.88 4.28 4.75 5.23 ns divide-by-2 mode, dcs enabled full 1.6 1.6 ns divide-by-3 through divide-by-8 modes, dcs enabled full 0.8 0.8 ns data output parameters (data, fd) cmos noninterleaved modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 1.6 3.9 6.2 1.6 3.9 6.2 ns dco propagation delay (t dco ) full 4.0 5.4 7.3 4.0 5.4 7.3 ns setup time (t s ) full 14.0 11.0 ns hold time (t h ) full 11.0 8.0 ns cmos noninterleaved modedrvdd = 3.3 v data propagation delay (t pd ) 2 full 1.9 4.1 6.4 1.9 4.1 6.4 ns dco propagation delay (t dco ) full 4.4 5.8 7.7 4.4 5.8 7.7 ns setup time (t s ) full 14.2 11.2 ns hold time (t h ) full 10.8 7.8 ns cmos interleaved and iq modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 1.6 3.9 6.2 1.6 3.9 6.2 ns dco propagation delay (t dco ) full 3.4 4.8 6.7 3.4 4.8 6.7 ns setup time (t s ) full 7.15 5.65 ns hold time (t h ) full 5.35 3.85 ns cmos interleaved and iq modedrvdd = 3.3 v data propagation delay (t pd ) 2 full 1.9 4.1 6.4 1.9 4.1 6.4 ns dco propagation delay (t dco ) full 3.8 5.2 7.1 3.8 5.2 7.1 ns setup time (t s ) full 7.35 5.85 ns hold time (t h ) full 5.15 3.65 ns lvds modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 2.5 4.8 7.0 2.5 4.8 7.0 ns dco propagation delay (t dco ) full 3.7 5.3 7.3 3.7 5.3 7.3 ns pipeline delay (latency) nco, fir, f s /8 mix disabled full 38 38 cycles pipeline delay (latency) nco enabled, fir and f s /8 mix disabled (complex output mode) full 38 38 cycles pipeline delay (latency) nco, fir, and f s /8 mix enabled full 109 109 cycles aperture delay (t a ) full 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 ps rms wake-up time 3 full 350 350 us out-of-range recovery time full 2 2 cycles 1 conversion rate is the clock rate after the divider. 2 output propagation delay is measured from clk 50% transition to data 50% transition, with a 5 pf load. 3 wake-up time is dependent on the value of the decoupling capacitors.
ad6655 rev. 0 | page 14 of 84 switching specificationsad6655bcpz-125/ad6655bcpz-150 table 8. ad6655bcpz-125 ad6655bcpz-150 parameter temp min typ max min typ max unit clock input parameters input clock rate full 625 625 mhz conversion rate 1 dcs enabled full 20 125 20 150 msps dcs disabled full 10 125 10 150 msps clk perioddivide-by-1 mode (t clk ) full 8 6.66 ns clk pulse width high (t clkh ) divide-by-1 mode, dcs enabled full 2.4 4 5.6 2.0 3.33 4.66 ns divide-by-1 mode, dcs disabled full 3.6 4 4.4 3.0 3.33 3.66 ns divide-by-2 mode, dcs enabled full 1.6 1.6 ns divide-by-3 through divide-by-8 modes, dcs enabled full 0.8 0.8 ns data output parameters (data, fd) cmos noninterleaved modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 1.6 3.9 6.2 1.6 3.9 6.2 ns dco propagation delay (t dco ) full 4.0 5.4 7.3 4.0 5.4 7.3 ns setup time (t s ) full 9.5 8.16 ns hold time (t h ) full 6.5 5.16 ns cmos noninterleaved modedrvdd = 3.3 v data propagation delay (t pd ) 2 full 1.9 4.1 6.4 1.9 4.1 6.4 ns dco propagation delay (t dco ) full 4.4 5.8 7.7 4.4 5.8 7.7 ns setup time (t s ) full 9.7 8.36 ns hold time (t h ) full 6.3 4.96 ns cmos interleaved and iq modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 1.6 3.9 6.2 1.6 3.9 6.2 ns dco propagation delay (t dco ) full 3.4 4.8 6.7 3.4 4.8 6.7 ns setup time (t s ) full 4.9 4.23 ns hold time (t h ) full 3.1 2.43 ns cmos interleaved and iq modedrvdd = 3.3 v data propagation delay (t pd ) 2 full 1.9 4.1 6.4 1.9 4.1 6.4 ns dco propagation delay (t dco ) full 3.8 5.2 7.1 3.8 5.2 7.1 ns setup time (t s ) full 5.1 4.43 ns hold time (t h ) full 2.9 2.23 ns lvds modedrvdd = 1.8 v data propagation delay (t pd ) 2 full 2.5 4.8 7.0 2.5 4.8 7.0 ns dco propagation delay (t dco ) full 3.7 5.3 7.3 3.7 5.3 7.3 ns pipeline delay (latency) nco, fir, f s /8 mix disabled full 38 38 cycles pipeline delay (latency) nco enabled; fir and f s /8 mix disabled (complex output mode) full 38 38 cycles pipeline delay (latency) nco, fir, and f s /8 mix enabled full 109 109 cycles aperture delay (t a ) full 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 ps rms wake-up time 3 full 350 350 us out-of-range recovery time full 3 3 cycles 1 conversion rate is the clock rate after the divider. 2 output propagation delay is measured from clk 50% transition to data 50% transition, with a 5 pf load. 3 wake-up time is dependent on the value of the decoupling capacitors.
ad6655 rev. 0 | page 15 of 84 timing specifications table 9. parameter conditions min typ max unit sync timing requirements t ssync sync to the rising edge of clk setup time 0.24 ns t hsync sync to the rising edge of clk hold time 0.4 ns spi timing requirements t ds setup time between the data and th e rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t low minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns sport timing requirements t cssclk delay from rising edge of clk+ to rising edge of smi sclk 3.2 4.5 6.2 ns t sslksdo delay from rising edge of smi sclk to smi sdo ?0.4 0 +0.4 ns t ssclksdfs delay from rising edge of smi sclk to smi sdfs ?0.4 0 +0.4 ns timing diagrams 06709-109 t h t s clk+ decimated cmos data decimated fd data channel a/b fd bits channel a/b fd bits channel a/b fd bits channel a/b data bits channel a/b data bits channel a/b data bits channel a/b fd bits channel a/b fd bits channel a/b fd bits decimated dcoa/dcob t pd t dco figure 2. decimated noninterleaved cmos mode data and fast detect output timing (fast detect mode select bits = 000) t s t pd t dco t h clk+ decimated cmos data channel a/b data bits channel a/b data bits decimated fd data channel a/b fd bits channel a/b fd bits decimated dcoa/dcob channel a/b data bits channel a/b fd bits 06709-012 figure 3. decimated noninterleaved cmos mode data and fast detect output timing (fast detect mode select bits = 001 through fas t detect mode select bits = 100)
ad6655 rev. 0 | page 16 of 84 t pd t dco t h t s clk+ decimated interleaved cmos data channel b: data channel a: data channel b: data channel b: data channel a: data channel b: fd bits channel a: fd bits channel b: fd bits channel b: fd bits channel a: fd bits decimated interleaved fd data decimated dco channel a: data channel a: fd bits 06709-013 figure 4. decimated interlea ved cmos mode data and fast detect output timing t pd t dco t h t s clk+ decimated cmos iq output data channel a/b: i data channel a/b: q data channel a/b: q data channel a/b: i data channel a/b: q data channel a/b: fd bits channel a/b: fd bits channel a/b: fd bits channel a/b: fd bits channel a/b: fd bits cmos fd data decimated dcoa/dcob channel a/b: i data channel a/b: fd bits 06709-014 figure 5. decimated iq mode cmos data and fast detect output timing t pd t dco clk? clk+ lvds data channel a: data channel b: data channel a: data lvds fast det dco? dco+ channel b: data channel a: fd channel b: fd channel a: fd channel b: fd channel a: data channel a: fd 06709-015 figure 6. decimated interlea ved lvds mode data and fast detect output timing t ssync t hsync sync clk+ 06709-016 figure 7. sync timing inputs
ad6655 rev. 0 | page 17 of 84 t cssclk t ssclksdfs t ssclksdfs clk+ clk? s mi sclk smi sdfs smi sdo data data 06709-017 figure 8. signal monito r sport output timing
ad6655 rev. 0 | page 18 of 84 absolute maximum ratings table 10. parameter rating electrical avdd, dvdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +3.9 v agnd to drgnd ?0.3 v to +0.3 v vin+a/vin+b, vin-a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to +3.9 v sync to agnd ?0.3 v to +3.9 v vref to agnd ?0.3 v to avdd + 0.2 v sense to agnd ?0.3 v to avdd + 0.2 v cml to agnd ?0.3 v to avdd + 0.2 v rbias to agnd ?0.3 v to avdd + 0.2 v csb to agnd ?0.3 v to +3.9 v sclk/dfs to drgnd ?0.3 v to +3.9 v sdio/dcs to drgnd ?0.3 v to drvdd + 0.3 v smi sdo/oeb to drgnd ?0.3 v to drvdd + 0.3 v smi sclk/pdwn to drgnd ?0.3 v to drvdd + 0.3 v smi sdfs to drgnd ?0.3 v to drvdd + 0.3 v d0a/d0b through d13a/d13b to drgnd ?0.3 v to drvdd + 0.3 v fd0a/fd0b through fd3a/fd3b to drgnd ?0.3 v to drvdd + 0.3 v dcoa/dcob to drgnd ?0.3 v to drvdd + 0.3 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ?65c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 11. thermal resistance package type airflow velocity (m/s) ja 1, 2 jc 1, 3 jb 1, 4 unit 0 18.8 0.6 6.0 c/w 1.0 16.5 c/w 64-lead lfcsp 9 mm 9 mm (cp-64-3) 2.0 15.8 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). typical ja is specified for a 4-layer pcb with solid ground plane. as shown, airflow increases heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the ja . esd caution
ad6655 rev. 0 | page 19 of 84 pin configurations a nd function descriptions 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d5a d6a d7a drgnd drvdd d8a d9a dvdd d10a d11a d12a d13a (msb) fd0a fd1a fd2a fd3a 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 drgnd d5b d4b d3b d2b d1b d0b (lsb) dvdd fd3b fd2b fd1b fd0b sync csb clk? clk+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 drvdd d6b d7b d8b d9b d10b d11b d12b d13b (msb) dcob dcoa d0a (lsb) d1a d2a d3a d4a sclk/dfs sdio/dcs avdd avdd vin+b vin?b rbias cml sense vref vin?a vin+a avdd smi sdfs smi sclk/pdwn smi sdo/oeb 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 pin 1 indicator ad6655 parallel cmos top view (not to scale) exposed paddle, pin 0 (bottom of package) 06709-002 figure 9. lfcsp parallel cmos pin configuration (top view) table 12. pin function descriptions (parallel cmos mode) pin no. mnemonic type description adc power supplies 20, 64 drgnd ground digital output ground. 1, 21 drvdd supply digital output driver supply (1.8 v to 3.3 v). 24, 57 dvdd supply digital power supply (1.8 v nominal). 36, 45, 46 avdd supply analog power supply (1.8 v nominal). 0 agnd ground analog ground. pin 0 is the expo sed thermal pad on the bottom of the package. adc analog 37 vin+a input differential analog input pin (+) for channel a. 38 vin?a input differential analog input pin (?) for channel a. 44 vin+b input differential analog input pin (+) for channel b. 43 vin?b input differential analog input pin (?) for channel b. 39 vref input/output voltage reference input/output. 40 sense input voltage reference mode select. (see table 15 for details.) 42 rbias input/output external reference bias resistor. 41 cml output common-mode level bi as output for analog inputs. 49 clk+ input adc clock inputtrue. 50 clk? input adc clock inputcomplement. adc fast detect outputs 29 fd0a output channel a fast detect indicator. (see table 21 for details.) 30 fd1a output channel a fast detect indicator. (see table 21 for details.) 31 fd2a output channel a fast detect indicator. (see table 21 for details.) 32 fd3a output channel a fast detect indicator. (see table 21 for details.) 53 fd0b output channel b fast detect indicator. (see table 21 for details.) 54 fd1b output channel b fast detect indicator. (see table 21 for details.) 55 fd2b output channel b fast detect indicator. (see table 21 for details.) 56 fd3b output channel b fast detect indicator. (see table 21 for details.) digital input 52 sync input digital synchronization pin. slave mode only.
ad6655 rev. 0 | page 20 of 84 pin no. mnemonic type description digital outputs 12 d0a (lsb) output channel a cmos output data. 13 d1a output channel a cmos output data. 14 d2a output channel a cmos output data. 15 d3a output channel a cmos output data. 16 d4a output channel a cmos output data. 17 d5a output channel a cmos output data. 18 d6a output channel a cmos output data. 19 d7a output channel a cmos output data. 22 d8a output channel a cmos output data. 23 d9a output channel a cmos output data. 25 d10a output channel a cmos output data. 26 d11a output channel a cmos output data. 27 d12a output channel a cmos output data. 28 d13a (msb) output channel a cmos output data. 58 d0b (lsb) output channel b cmos output data. 59 d1b output channel b cmos output data. 60 d2b output channel b cmos output data. 61 d3b output channel b cmos output data. 62 d4b output channel b cmos output data. 63 d5b output channel b cmos output data. 2 d6b output channel b cmos output data. 3 d7b output channel b cmos output data. 4 d8b output channel b cmos output data. 5 d9b output channel b cmos output data. 6 d10b output channel b cmos output data. 7 d11b output channel b cmos output data. 8 d12b output channel b cmos output data. 9 d13b (msb) output channel b cmos output data. 11 dcoa output channel a data clock output. 10 dcob output channel b data clock output. spi control 48 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 47 sdio/dcs input/output spi serial data i/o/duty cycle stabilizer pin in external pin mode. 51 csb input spi chip select. active low. signal monitor port 33 smi sdo/oeb input/output signal monitor serial data output/output enable input (active low) in external pin mode. 35 smi sdfs output signal monitor serial data frame sync. 34 smi sclk/pdwn input/output signal monitor serial clock output/power- down input (active high) in external pin mode.
ad6655 rev. 0 | page 21 of 84 pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d7+ d8? d8+ drgnd drvdd d9? d9+ dvdd d10? d10+ d11? d11+ d12? d12+ d13? (msb) d13+ (msb) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 drgnd d0+ (lsb) d0? (lsb) fd3+ fd3? fd2+ fd2? dvdd fd1+ fd1? fd0+ fd0? sync csb clk? clk+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 drvdd d1? d1+ d2? d2+ d3? d3+ d4? d4+ dco? dco+ d5? d5+ d6? d6+ d7? sclk/dfs sdio/dcs avdd avdd vin+b vin?b rbias cml sense vref vin?a vin+a avdd smi sdfs smi sclk/pdwn smi sdo/oeb 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad6655 parallel lvds top view (not to scale) exposed paddle, pin 0 (bottom of package) 06709-003 figure 10. lfcsp interleaved parallel lvds pin configuration (top view) table 13. pin function descriptions (interleaved parallel lvds mode) pin no. mnemonic type description adc power supplies 20, 64 drgnd ground digital output ground. 1, 21 drvdd supply digital output driver supply (1.8 v to 3.3 v). 24, 57 dvdd supply digital power supply (1.8 v nominal.) 36, 45, 46 avdd supply analog power supply (1.8 v nominal.) 0 agnd ground analog ground. pin 0 is the expo sed thermal pad on the bottom of the package. adc analog 37 vin+a input differential analog input pin (+) for channel a. 38 vin?a input differential analog input pin (?) for channel a. 44 vin+b input differential analog input pin (+) for channel b. 43 vin?b input differential analog input pin (?) for channel b. 39 vref input/output voltage reference input/output. 40 sense input voltage reference mode select. see table 15 for details. 42 rbias input/output external reference bias resistor. 41 cml output common-mode level bi as output for analog inputs. 49 clk+ input adc clock inputtrue. 50 clk? input adc clock inputcomplement. adc fast detect outputs 54 fd0+ output channel a/channel b lvds fast detect indicator 0true. see table 21 for details. 53 fd0- output channel a/channel b lvds fast detect indicator 0complement. see table 21 for details. 56 fd1+ output channel a/channel b lvds fast detect indicator 1true. see table 21 for details. 55 fd1? output channel a/channel b lvds fast detect indicator 1complement. see table 21 for details. 59 fd2+ output channel a/channel b lvds fast detect indicator 2true see table 21 for details. 58 fd2? output channel a/channel b lvds fast detect indicator 2complement. see table 21 for details. 61 fd3+ output channel a/channel b lvds fast detect indicator 3true. see table 21 for details. 60 fd3? output channel a/channel b lvds fast detect indicator 3complement. see table 21 for details.
ad6655 rev. 0 | page 22 of 84 pin no. mnemonic type description digital input 52 sync input digital synchronization pin. slave mode only. digital outputs 63 d0+ (lsb) output channel a/channel b lvds output data 0true. 62 d0? (lsb) output channel a/channel b lvds output data 0complement. 3 d1+ output channel a/channel b lvds output data 1true. 2 d1? output channel a/channel b lvds output data 1complement. 5 d2+ output channel a/channel b lvds output data 2true. 4 d2? output channel a/channel b lvds output data 2complement. 7 d3+ output channel a/channel b lvds output data 3true. 6 d3? output channel a/channel b lvds output data 3complement. 9 d4+ output channel a/channel b lvds output data 4true. 8 d4? output channel a/channel b lvds output data 4complement. 13 d5+ output channel a/channel b lvds output data 5true. 12 d5? output channel a/channel b lvds output data 5complement. 15 d6+ output channel a/channel b lvds output data 6true. 14 d6? output channel a/channel b lvds output data 6complement. 17 d7+ output channel a/channel b lvds output data 7true. 16 d7? output channel a/channel b lvds output data 7complement. 19 d8+ output channel a/channel b lvds output data 8true. 18 d8? output channel a/channel b lvds output data 8complement. 23 d9+ output channel a/channel b lvds output data 9true. 22 d9? output channel a/channel b lvds output data 9complement. 26 d10+ output channel a/channel b lvds output data 10true. 25 d10? output channel a/channel b lvds output data 10complement. 28 d11+ output channel a/channel b lvds output data 11true. 27 d11? output channel a/channel b lvds output data 11complement. 30 d12+ output channel a/channel b lvds output data 12true. 29 d12? output channel a/channel b lvds output data 12complement. 32 d13+ (msb) output channel a/channel b lvds output data 13true. 31 d13? (msb) output channel a/channe l b lvds output data 13complement. 11 dco+ output channel a/channel b lvds data clock outputtrue. 10 dco? output channel a/channel b lv ds data clock outputcomplement. spi control 48 sclk/dfs input spi serial clock/data fo rmat select pin in external pin mode. 47 sdio/dcs input/output spi serial data i/o/du ty cycle stabilizer in external pin mode. 51 csb input spi chip select (active low). signal monitor port 33 smi sdo/oeb input/output signal monitor serial data output/output enable input (active low) in external pin mode. 35 smi sdfs output signal monitor serial data frame sync. 34 smi sclk/pdwn input/output signal monitor serial clock output/power- down input (active high) in external pin mode
ad6655 rev. 0 | page 23 of 84 equivalent circuits v in 06709-004 figure 11. equivalent analog input circuit 1.2v 10k ? 10k? c lk+ clk? avdd 06709-005 figure 12. equivalent clock lnput circuit drvdd drgnd 0 6709-006 figure 13. equivalent digital output circuit s dio/dcs 1k ? 26k? drvdd drvdd 06709-007 figure 14. equivalent sdio/dcs circuit or smi sdfs circuit sclk/dfs 1k? 26k ? 06709-008 figure 15. equivalent sclk/dfs input circuit sense 1k? 06709-009 figure 16. equivalent sense circuit csb 1k ? 26k ? avdd 06709-010 figure 17. equivalent csb input circuit v ref avdd 6k ? 06709-011 figure 18. equivalent vref circuit .
ad6655 rev. 0 | page 24 of 84 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) typical performance characteristics avdd = 1.8 v, dvdd = 1.8 v, drvdd = 1.8 v, sample rate = 150 msps, dcs enabled, 1.0 v internal reference, 2 v p-p differential input, vin = ?1.0 dbfs, 64k sample, t a = 25c, nco enabled, fir filter enabled, unless otherwise noted. in the fft plots that follow, the location of the second and third harmonics is noted when they fall in the pass band of the filter. 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 150msps 2.4mhz @ ?1dbfs snr = 74.7dbc (75.7dbfs) sfdr = 86.5dbc f nco = 18.75mhz second harmonic third harmonic 06709-018 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) figure 19. ad6655-150 single-tone fft with f in = 2.4 mhz, f nco = 18.75 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 150msps 30.3mhz @ ?1dbfs snr = 74.8dbc (75.8dbfs) sfdr = 100dbc f nco = 24mhz 06709-019 figure 20. ad6655-150 single-tone fft with f in = 30.3 mhz, f nco = 24 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 06709-020 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 150msps 140.1mhz @ ?1dbfs snr = 73.7dbc (74.7dbfs) sfdr = 82.8dbc f nco = 126mhz second harmonic third harmonic 06709-021 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 150msps 140.1mhz @ ?1dbfs snr = 74.3dbc (75.3dbfs) sfdr = 83.3dbc f nco = 56mhz third harmonic figure 21. ad6655-150 single-tone fft with f in = 70.1 mhz, f nco = 56 mhz figure 22. ad6655-150 single-tone fft with f in = 140.1 mhz, f nco = 126 mhz 150msps 220.1mhz @ ?1dbfs snr = 71.8dbc (72.8dbfs) sfdr = 81.4dbc f nco = 205mhz third harmonic 06709-022 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) figure 23. ad6655-150 single-tone fft with f in = 220.1 mhz, f nco = 205 mhz 150msps 332.1mhz @ ?1dbfs snr = 71.7dbc (72.7dbfs) sfdr = 95.0dbc f nco = 321.5mhz 06709-023 figure 24. ad6655-150 single-tone fft with f in = 332.1 mhz, f nco = 321.5 mhz
ad6655 rev. 0 | page 25 of 84 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 150msps 445.1mhz @ ?1dbfs snr = 67.4dbc (65.4dbfs) sfdr = 74.1dbc f nco = 429mhz second harmonic third harmonic 06709-024 25 20 15 10 5 amplitude (dbfs) frequency (mhz) figure 25. ad6655-150 single-tone fft with f in = 445.1 mhz, f nco = 429 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 0 125msps 2.4mhz @ ?1dbfs snr = 74.5dbc (75.5dbfs) sfdr = 87.8dbc f nco = 15.75mhz second harmonic third harmonic 06709-025 25 20 15 10 5 amplitude (dbfs) frequency (mhz) figure 26. ad6655-125 single-tone fft with f in =2.4 mhz, f nco = 15.75 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 0 06709-026 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 0 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 125msps 70.3mhz @ ?1dbfs snr = 74.6dbc (75.6dbfs) sfdr = 86.1dbc f nco = 78mhz third harmonic 06709-027 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 0 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 125msps 30.3mhz @ ?1dbfs snr = 74.7dbc (75.7dbfs) sfdr = 89.6dbc f nco = 21mhz third harmonic figure 27. ad6655-125 single-tone fft with f in = 30.3 mhz, f nco = 21 mhz figure 28. ad6655-125 single-tone fft with f in = 70.3 mhz, f nco = 78 mhz 125msps 140.1mhz @ ?1dbfs snr = 74.1dbc (75.1dbfs) sfdr = 90.3dbc f nco = 142mhz third harmonic 06709-028 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 0 25 20 15 10 5 amplitude (dbfs) frequency (mhz) figure 29. ad6655-125 single-tone fft with f in = 140.1 mhz, f nco = 142 mhz 125msps 220.1mhz @ ?1dbfs snr = 73.4dbc (74.4dbfs) sfdr = 90.2dbc f nco = 231mhz 06709-029 figure 30. ad6655-125 single-tone fft with f in = 220.1 mhz, f nco = 231 mhz
ad6655 rev. 0 | page 26 of 84 120 0 20 40 60 80 100 ?90 0?10?20?30?40?50?60?70 ?80 snr/sfdr (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) snr (dbfs) snr (dbc) 85db reference line 06709-030 figure 31. ad6655-150 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 2.4 mhz, f nco = 18.75 mhz 120 0 20 40 60 80 100 ?90 0?10?20?30?40?50?60?70 ?80 snr/sfdr (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) snr (dbfs) snr (dbc) 85db reference line 06709-031 figure 32. ad6655-150 single-ton e snr/sfdr vs. input amplitude (a in ) with f in = 98.12 mhz, f nco = 100.49 mhz 95 90 85 80 75 70 65 60 04 5 0 400350 30025020015010050 snr/sfdr (dbc) input frequency (mhz) sfdr = +25c sfdr = +85c sfdr = ?40c snr = +25c snr = +85c snr = ?40c 06709-032 figure 33. ad6655-125 single-tone snr/sfdr vs. input frequency (f in ) and temperature with drvdd = 1.8 v 95 90 85 80 75 70 65 60 04 400350 30025020015010050 snr/sfdr (dbc) input frequency (mhz) sfdr = +25c sfdr = +85c sfdr = ?40c 5 0 snr = +25c snr = +85c snr = ?40c 06709-033 figure 34. ad6655-125 single-tone snr/sfdr vs. input frequency (f in ) and temperature with drvdd = 3.3 v ? 1.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 0.5 0 0.1 0.2 0.3 0.4 ?40 80 60 40 20 0 ?20 gain error (%fsr) offset error (%fsr) temperature (c) 06709-034 offset gain figure 35. ad6655-150 gain and offset vs. temperature 0 ?120 ?100 ?80 ?60 ?40 ?20 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) imd3 (dbc) 06709-035 figure 36. ad6655-150 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 29.12 mhz, f in2 = 32.12 mhz, f s = 150 msps, f nco = 22 mhz
ad6655 rev. 0 | page 27 of 84 0 ?120 ?100 ?80 ?60 ?40 ?20 ?90 ?78 ?66 ?54 ?42 ?30 ?18 ?6 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbfs) imd3 (dbc) 06709-036 figure 37. ad6655-150 two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 169.12 mhz, f in2 = 172.12 mhz, f s = 150 msps, f nco = 177 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 5 10 15 20 25 30 06709-037 amplitude (dbfs) frequency (mhz) figure 38. ad6655-125, two 64k wcdma carriers with f in = 170 mhz, f s = 122.88 mhz, f nco = 168.96 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 5 06709-038 5 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 150msps 29.12mhz @ ?7dbfs 32.12mhz @ ?7dbfs sfdr = 89.1dbc (96.1dbfs) f nco = 22mhz figure 39. ad6655-150 two-tone fft with f in1 = 29.12 mhz, f in2 = 32.12 mhz, f s = 150 msps, f nco = 22 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 150msps 169.12mhz @ ?7dbfs 172.12mhz @ ?7dbfs sfdr = 85.5dbc (92.5dbfs) f nco = 177mhz 06709-039 figure 40. ad6655-150 two tone fft with f in1 = 169.12 mhz, f in2 = 172.12 mhz, f s = 150 msps, f nco = 177 mhz 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 03 30.0 22.5 15.0 7.5 amplitude (dbfs) frequency (mhz) 7 . 5 npr = 64.5dbc notch @ 18.5mhz notch width = 3mhz 06709-040 figure 41. ad6655-150 noise power ratio (npr) 95 85 75 65 0 25 50 75 100 125 150 06709-041 snr/sfdr (dbc) sample rate (msps) sfdr (dbc) snr (dbc) figure 42. ad6655-150 single-tone snr/sfdr vs. sample rate (f s ) with f in = 2.3 mhz
ad6655 rev. 0 | page 28 of 84 12 0 2 4 6 8 10 number of hits (1m) output code n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 0.85 lsb rms 06709-042 figure 43. ad6655 grounded input histogram 90 85 80 75 70 snr/sfdr (dbc) duty cycle (%) sfdr dcs on snr dcs on sfdr dcs off snr dcs off 20 30 40 50 60 70 80 06709-043 figure 44. ad6655-150 snr/sfdr vs. duty cycle with f in = 30.3 mhz, f nco = 45 mhz 90 85 80 75 65 70 snr/sfdr (dbc) input common-mode voltage (v) snr sfdr 0.2 0.4 0.6 0.8 1.0 1.2 1.4 06709-044 figure 45. ad6655-150 snr/sfdr vs. input common mode (v cm ) with f in = 30.3 mhz, f nco = 45 mhz
ad6655 rev. 0 | page 29 of 84 theory of operation the ad6655 has two analog input channels, two decimating channels, and two digital output channels. the intermediate frequency (if) input signal passes through several stages before appearing at the output port(s) as a filtered, decimated digital signal. the dual adc design can be used for diversity reception of signals, where the adcs operate identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample any f s /2 frequency segment from dc to 150 mhz using appropriate low- pass or band-pass filtering at the adc inputs with little loss in adc performance. operation to 450 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. in nondiversity applications, the ad6655 can be used as a base- band receiver, where one adc is used for i input data, and the other is used for q input data. synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. the nco phase can be set to produce a known offset relative to another channel or device. programming and control of the ad6655 are accomplished using a 3-bit spi-compatible serial interface. adc architecture ad6655 architecture consists of a front-end sample-and-hold amplifier (sha) followed by a pipelined, switched-capacitor adc. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the pipelined archi- tecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor digital- to-analog converter (dac) and an interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sha that can be ac- or dc-coupled in differential or single-ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power-down, the output buffers go into a high impedance state. analog input considerations the analog input to the ad6655 is a differential switched- capacitor sha that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively switches the sha between sample mode and hold mode (see figure 46 ). when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within 1/2 of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in if undersampling applications, any shunt capacitors should be reduced. in combination with the driving source impedance, the shunt capacitors limit the input bandwidth. refer to appli- cation note an-742, frequency domain response of switched- capacitor adcs ; application note an-827, a resonant approach to interfacing amplifiers to switched-capacitor adcs ; and the analog dialogue article, transformer-coupled front-end for wideband a/d converters, for more information on this subject (see www.analog.com ). in general, the precise values are dependent on the application. vin+ vin? c pin, par c pin, par c s c s c h c h h s s s s 06709-048 figure 46. switched-c apacitor sha input for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. an internal differential reference buffer creates positive and negative reference voltages that define the input span of the adc core. the output common mode of the reference buffer is set to v cmref (approximately 1.6 v ). input common mode the analog inputs of the ad6655 are not internally dc biased. in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.55 avdd is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see figure 45 ).
ad6655 rev. 0 | page 30 of 84 an on-board common-mode voltage reference is included in the design and is available from the cml pin. optimum perform- ance is achieved when the common-mode voltage of the analog input is set by the cml pin voltage (typically 0.55 avdd). differential input configurations optimum performance is achieved while driving the ad6655 in a differential input configuration. for baseband applications, the ad8138 , ada4937-2 , and ada4938-2 differential drivers provide excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set with the cml pin of the ad6655 (see figure 47 ), and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. avdd 1v p-p 49.9 ? 523 ? 0.1f r r c 499 ? 499 ? 499 ? ad8138 ad6655 vin+ vin? cml 06709-049 figure 47. differential input configuration using the ad8138 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 48 . to bias the analog input, the cml voltage can be connected to the center tap of the secondary winding of the transformer. 2v p-p 49.9 ? 0.1f r r c ad6655 vin+ vin? cml 06709-050 figure 48. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few megahertz (mhz). excessive signal power can also cause core saturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad6655. for applications where snr is a key parameter, differential double balun coupling is the recommended input configuration (see figure 49 ). an alternative to using a transformer-coupled input at frequencies in the second nyquist zone is to use the ad8352 differential driver is shown in figure 50 . see the ad8352 data sheet for more information. in addition, if the application requires an amplifier with variable gain, the ad8375 or ad8376 digital variable gain amplifiers (dvgas) provide good performance driving the ad6655. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and source impedance and may need to be reduced or removed. table 14 displays recom- mended values to set the rc network. however, these values are dependent on the input signal and should be used only as a starting guide. table 14. example rc network frequency range (mhz) r series (, each) c differential (pf) 0 to 70 33 15 70 to 200 33 5 200 to 300 15 5 >300 15 open ad6655 r 0.1 f 0.1 f 2v p-p vin+ vin? cml c r 0.1f s 0.1f 25 ? 25 ? s p a p 06709-051 figure 49. differential double balun input configuration ad6655 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 14 0.1f 8, 13 v cc 200 ? 200? analog input analog input 06709-052 figure 50. differential input configuration using the ad8352
ad6655 rev. 0 | page 31 of 84 single-ended input configuration a single-ended input can provide adequate performance in cost-sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common- mode swing. if the source impedances on each input are matched, there should be little effect on snr performance. figure 51 shows a typical single-ended input configuration. 2v p-p r r c 49.9 ? 0.1f 10f 10f 0.1f av dd 1k? 1k ? 1k ? 1k ? ad6655 a v dd vin+ vin? 06709-053 figure 51. single-ended input configuration voltage reference a stable and accurate voltage reference is built into the ad6655. the input range can be adjusted by varying the reference voltage applied to the ad6655, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. the various reference modes are summarized in the sections that follow. the reference decoupling section describes the best practices pcb layout of the reference. internal reference connection a comparator within the ad6655 detects the potential at the sense pin and configures the reference into four possible modes, which are summarized in table 15 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 52 ), setting vref to 1.0 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected externally to the chip, as shown in figure 53 , the switch again sets to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as follows: ? ? ? ? ? ? += 15. 0 the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. vref sense 0.5v ad6655 select logic 0.1f 1.0f vin?a/vin?b vin+a/vin+b adc core 0 6709-054 figure 52. internal reference configuration 0.5v ad6655 select logic vin?a/vin?b vin+a/vin+b adc core vref sense 0.1f 1.0f r2 r1 0 6709-055 figure 53. programmable reference configuration table 15. reference configuration summary selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to vref ? ? ? ? ? ? + r1 r2 15.0 (see figure 53 ) 2 vref internal fixed reference agnd to 0.2 v 1.0 2.0
ad6655 rev. 0 | page 32 of 84 2 . 0 if the internal reference of the ad6655 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 54 depicts how the internal reference voltage is affected by loading. 0 ?1.25 0 load current (ma) reference voltage error (%) ?0.25 ?0.50 ?0.75 ?1.00 0.5 1.0 1.5 vref = 0.5v vref = 1.0v 0 6709-056 figure 54. vref accuracy vs. load external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 55 shows the typical drift characteristics of the internal reference in both 1.0 v and 0.5 v modes. 2.5 ?2.5 ?40 temperature (c) reference voltage error (mv) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?200 20406080 06709-057 figure 55. typical vref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 6 k load (see figure 18 ). the internal buffer generates the positive and negative full-scale references for the adc core. therefore, the external reference must be limited to a maximum of 1.0 v. clock input considerations for optimum performance, the ad6655 sample clock inputs, clk+ and clk?, should be clocked with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 56 ) and require no external bias. 1.2v a vdd 2pf 2pf clk? clk+ 0 6709-058 figure 56. equivalent clock input circuit clock input options the ad6655 has a very flexible clock input structure. clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 57 and figure 58 show two preferred methods for clocking the ad6655 (at clock rates to up to 625 mhz). a low jitter clock source is converted from a single-ended signal to a differential signal using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad6655 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad6655, while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc ad6655 mini-circuits ? adt1?1wt, 1:1z xfmr 06709-059 figure 57. transformer coupled differential clock (up to 200 mhz) 0.1f 0.1f 1nf clock input 1nf 50? clk? clk+ adc ad6655 schottky diodes: hsms2822 06709-157 figure 58. balun-coupled differential clock (up to 625 mhz) if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins as shown in figure 59 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 clock drivers offer excellent jitter performance.
ad6655 rev. 0 | page 33 of 84 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad951x pecl driver 50k ? 50k ? clk? clk+ adc ad6655 clock input clock input 06709-060 figure 59. differential pecl sample clock (up to 625 mhz) a third option is to ac-couple a differential lvds signal to the sample clock input pins, as shown in figure 60 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? 50k ? clk? clk+ adc ad6655 clock input clock input ad951x lvds driver 06709-061 figure 60. differential lvds sample clock (up to 625 mhz) in some applications, it may be acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applica- tions, the clk+ pin should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 61 ). clk+ can be driven directly from a cmos gate. although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages of up to 3.6 v, making the selection of the drive logic voltage very flexible. optional 100? 0.1f 0.1f 0.1f 39k? 50? clk? clk+ adc ad6655 v cc 1k? 1k? clock input ad951x cmos driver 06709-062 figure 61. single-ended 1.8 v cmos sample clock (up to 150 msps) optional 100 ? 0.1f 0.1f 0.1f v cc 50 ? clk? clk+ adc ad6655 1k? 1k? clock input ad951x cmos driver 06709-063 figure 62. single-ended 3.3 v cmos sample clock (up to 150 msps) input clock divider the ad6655 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. if a divide ratio other than 1 is selected, the duty cycle stabilizer is auto- matically enabled. the ad6655 clock divider can be synchronized using the external sync input. bit 1 and bit 2 of register 0x100 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad6655 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad6655. noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs on, as shown in figure 44 . jitter on the rising edge of the input clock is still of paramount concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz nominally. the loop has a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time period that the loop is not locked, the dcs loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calculated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ] )10/( lf snr ? in the equation, the rms aperture jitter represents the root- mean-square of all jitter sources, which include the clock input, the analog input signal, and the adc aperture jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 63 .
ad6655 rev. 0 | page 34 of 84 75 70 65 60 55 50 45 1 10 100 1000 snr (dbc) input frequency (mhz) 3.00ps 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps 2.00ps 2.50ps measured 06709-064 figure 63. snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad6655. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. refer to application note an501 and application note an756 for more information about jitter performance as it relates to adcs (see www.analog.com ). power dissipation and standby mode as shown in figure 64 through figure 67 , the power dissipated by the ad6655 is proportional to its sample rate. in cmos output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current (i drvdd ) can be calculated by i drvdd = v drvdd c load f clk n where n is the number of output bits (30, in the case of the ad6655, assuming the fd bits are inactive). this maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the nyquist frequency of f clk /2. in practice, the drvdd current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. reducing the capacitive load presented to the output drivers can minimize digital power consumption. the data in figure 64 through figure 67 was taken using the same operating conditions as those used for the typical performance characteristics , with a 5 pf load on each output driver. 1.50 1.25 1.00 0.75 0.50 0.25 0 0.6 i avdd i dvdd i drvdd 0.5 0.4 0.3 0.2 0.1 0 0 50 100 total power (w) supply current (a) 150 25 75 125 sample rate (msps) total power 06709-065 figure 64. ad6655-150 power and current vs. sample rate 1.50 1.25 1.00 0.75 0.50 0.25 0 0.6 0.5 i avdd i dvdd i drvdd 0.4 0.3 0.2 0.1 0 07 5 total power (w) supply current (a) 25 50 125 100 sample rate (msps) total power 06709-166 figure 65. ad6655-125 power and current vs. sample rate 1.25 1.00 0.75 0.50 0.25 0 0.5 0.4 i avdd i dvdd i drvdd 0.3 0.2 0.1 0 07 5 total power (w) supply current (a) 25 50 100 sample rate (msps) total power 06709-167 figure 66. ad6655-105 power and current vs. sample rate
ad6655 rev. 0 | page 35 of 84 1.00 0.75 0.50 0.25 0 0.4 iavdd idvdd idrvdd 0.3 0.2 0.1 0 06 0 total power (w) supply current (a) 20 40 80 sample rate (msps) total power 06709-168 figure 67. ad6655-80 power and current vs. sample rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high), the ad6655 is placed in power-down mode. in this state, the adc typically dissipates 2.5 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad6655 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. pdwn can be driven with 1.8 v logic, even when drvdd is at 3.3 v. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map register description section and application note an-877, interfacing to high speed adcs via spi at www.analog.com for additional details. digital outputs the ad6655 output drivers can be configured to interface with 1.8 v to 3.3 v cmos logic families by matching drvdd to the digital supply of the interfaced logic. alternatively, the ad6655 outputs can be configured for either ansi lvds or reduced drive lvds using a 1.8 v drvdd supply. in cmos output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applica- tions requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. the output data format can be selected for either offset binary or twos complement by setting the sclk/dfs pin when operating in the external pin mode (see table 16 ). as detailed in application note an-877, interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when using the spi control. table 16. sclk/dfs mode selection (external pin mode) voltage at pin sclk/dfs sdio/dcs agnd (default) offset binary dcs disabled avdd twos complement dcs enabled digital output enable function (oeb) the ad6655 has a flexible three-state ability for the digital output pins. the three-state mode is enabled using the smi sdo/oeb pin or through the spi interface. if the smi sdo/oeb pin is low, the output data drivers are enabled. if the smi sdo/oeb pin is high, the output data drivers are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that oeb is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. oeb can be driven with 1.8 v logic even when drvdd is at 3.3 v. when using the spi interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit (bit 4) in register 0x14. interleaved cmos mode setting bit 5 in register 0x14 enables interleaved cmos output mode. in this mode, output data is routed through port a with the adc channel a output data present on the rising edge of dco and the adc channel b output data present on the falling edge of dco. timing the ad6655 provides latched data with a pipeline delay that is dependent on which of the digital back end features are enabled. data outputs are available one propagation delay (t pd ) after the rising edge of the clock signal. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad6655. these transients can degrade converter dynamic performance. the lowest typical conversion rate of the ad6655 is 10 msps. at clock rates below 10 msps, dynamic performance may degrade. data clock output (dco) the ad6655 also provides data clock output (dco) intended for capturing the data in an external register. figure 2 through figure 6 show a graphical timing description of the ad6655 output modes.
ad6655 rev. 0 | page 36 of 84 table 17. output data format input (v) condition (v) offset binary output mode twos complement mode or vin+ C vinC < Cvref C 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 1 vin+ C vinC = Cvref 00 0000 0000 0000 10 0000 0000 0000 0 vin+ C vinC = 0 10 0000 0000 0000 00 0000 0000 0000 0 vin+ C vinC = +vref C 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 0 vin+ C vinC > +vref C 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 1
ad6655 rev. 0 | page 37 of 84 digital downconverter the ad6655 includes a digital proc essing section that provides filtering and reduces the output data rate. this digital processing section includes a numerically controlled oscillator (nco), a half-band decimating filter, an fir filter, and a second coarse nco (f adc /8 fixed value) for output frequency translation. each of these processing blocks (except the decimating half-band filter) has control lines that allow it to be independently enabled and disabled to provide the desired processing function. the digital downconverter can be configured to output either real data or complex output data. these blocks can be configured in five recommended combinations to implement different signal processing functions. downconverter modes table 18 details the recommended downconverter modes of operation in the ad6655. table 18. downconverter modes mode nco/filter output type 1 half-band filter only real 2 half-band filter and fir filter real 3 nco and half-band filter complex 4 nco, half-band filter, and fir filter complex 5 nco, half-band filter, fir filter, and f adc /8 nco real numerically controlled oscillator (nco) frequency translation is accomplished with an nco. each of the two processing channels shares a common nco. amplitude and phase dither can be enabled on chip to improve the noise and spurious performance of the nco. a phase offset word is available to create a known phase relationship between multiple ad6655s. because the decimation filter prevents usage of half the nyquist spectrum, a means is needed to translate the sampled input spectrum into the usable range of the decimation filter. to achieve this, a 32-bit, fine tuning, complex nco is provided. this nco/mixer allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. half-band decimating filter and fir filter the goal of the ad6655 digital filter block is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. the half-band filter is designed to operate as either a low-pass or high-pass filter and to provide greater than 100 db of alias protection for 22% of the input rate of the structure. for an adc sample rate of 150 msps, this provides a maximum usable bandwidth of 16.5 mhz when using the filter in real mode (nco bypassed) or a maximum usable bandwidth of 33.0 mhz when using the filter in the complex mode (nco enabled). the optional fixed-coefficient fir filter provides additional filtering capability to sharpen the half-band roll-off to enhance the alias protection. it removes the negative frequency images to avoid aliasing negative frequencies for real outputs. f adc /8 fixed-frequency nco a fixed f adc /8 nco is provided to translate the filtered, decimated signal from dc to f adc /8 to allow a real output. figure 68 to figure 71 show an example of a 20 mhz input as it is processed by the blocks of the ad6655. ?50 ?24 ?14 14 24 50 ?4 4 0 06709-066 figure 68. example ad6655 real 20 mhz bandwidth input signal centered at 14 mhz (f adc = 100 mhz) ?50 ?38 ?28 0 10 50 ?18 ?10 06709-067 figure 69. example ad6655 20 mhz bandwidth input signal tuned to dc using the nco (nco frequency = 14 mhz) ?50 ?38 ?28 0 10 50 ?18 ?10 06709-068 figure 70. example ad6655 20 mh z bandwidth input signal wth the negative image filtered by the half-band and fir filters ?50 0.25 22.5 12.5 50 0 6709-069 figure 71. example ad6655 20 mhz bandwidth input signal tuned to f adc /8 for real output
ad6655 rev. 0 | page 38 of 84 numerically controlled oscillator (nco) frequency translation this processing stage comprises a digital tuner consisting of a 32-bit complex numerically controlled oscillator (nco). the two channels of the ad6655 share a single nco. the nco is optional and can be bypassed by clearing bit 0 of register 0x11d. this nco block accepts a real input from the adc stage and outputs a frequency translated complex (i and q) output. the nco frequency is programmed in register 0x11e, register 0x11f, register 0x120, and register 0x121. these four 8-bit registers make up a 32-bit unsigned frequency programming word. frequencies between ?clk/2 and +clk/2 are represented using the following frequency words: ? 0x8000 0000 represents a frequency given by ?clk/2. ? 0x0000 0000 represents dc (frequency = 0 hz). ? 0x7fff ffff represents clk/2 ? clk/2 32 . use the following equation to calculate the nco frequency: clk clk f ffmod nco_freq ),( 2 32 = where: nco_freq is a 32-bit twos complement number representing the nco frequency register. f is the desired carrier frequency in hertz (hz). f clk is the ad6655 adc clock rate in hertz (hz). nco synchronization the ad6655 ncos within a single part or across multiple parts can be synchronized using the external sync input. bit 3 and bit 4 of register 0x100 allow the nco to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the nco to restart at the programmed phase offset value. phase offset the nco phase offset register at address 0x122 and address 0x123 adds a programmable offset to the phase accumulator of the nco. this 16-bit register is interpreted as a 16-bit unsigned integer. a 0x00 in this register corresponds to no offset, and a 0xffff corresponds to an offset of 359.995. each bit represents a phase change of 0.005. this register allows multiple ncos to be synchronized to produce outputs with predictable phase differences. use the following equation to calculate the nco phase offset value: nco _ phase = 2 16 phase /360 where: nco_phase is a decimal number equal to the 16-bit binary number to be programmed at register 0x122 and register 0x123. phase is the desired nco phase in degrees. nco amplitude and phase dither the nco block contains amplitude and phase dither to improve the spurious performance. amplitude dither improves performance by randomizing the amplitude quantization errors within the angular-to-cartesian conversion of the nco. this option reduces spurs at the expense of a slightly raised noise floor. with amplitude dither enabled, the nco has an snr of >93 db and an sfdr of >115 db. with amplitude dither disabled, the snr is increased to >96 db at the cost of sfdr performance, which is reduced to 100 db. the nco amplitude dither is recommended and is enabled by setting bit 1 of register 0x11d.
ad6655 rev. 0 | page 39 of 84 decimating half-band filter and fir filter the goal of the ad6655 half-band digital filter is to allow the sample rate to be reduced by a factor of 2 while rejecting aliases that fall into the band of interest. this filter is designed to operate as either a low-pass or a high-pass filter and to provide >100 db of alias protection for 11% of the input rate of the structure. used in conjunction with the nco and the fir filter, the half- band filter can provide an effective band-pass. for an adc sample rate of 150 msps, this provides a maximum usable bandwidth of 33 mhz. half-band filter coefficients the 19-tap, symmetrical, fixed-coefficient half-band filter has low power consumption due to its polyphase implementation. table 19 lists the coefficients of the half-band filter. the normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are also listed. coefficients not listed in table 19 are 0s. table 19. fixed coefficients for half-band filter coefficient number normalized coefficient decimal coefficient (20-bit) c0, c18 0.0008049 844 c2, c16 ?0.0059023 ?6189 c4, c14 0.0239182 25080 c6, c12 ?0.0755024 ?79170 c8, c10 0.3066864 321584 c9 0.5 524287 half-band filter features in the ad6655, the half-band filter cannot be disabled. the filter can be set for a low-pass or high-pass response. for a high- pass filter, bit 1 of register 0x103 should be set; for a low-pass response, this bit should be cleared. the low-pass response of the filter with respect to the normalized output rate is shown in figure 72 , and the high-pass response is shown in figure 73 . 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 0.2 0.3 0.4 amplitude (dbc) fraction of input sample rate 06709-070 figure 72. half-band filter low-pass response 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 0.2 0.3 0.4 amplitude (dbc) fraction of input sample rate 06709-071 figure 73. half-band filter high-pass response the half-band filter has a ripp le of 0.000182 db and a rejection of 100 db. for an alias rejection of 100 db, the alias protected bandwidth is 11% of the input sample rate. if both the i and the q paths are used, a complex bandwidth of 22% of the input rate is available. in the event of even nyquist zone sampling, the half-band filter can be configured to provide a spectral reversal. setting bit 2 high in address 0x103 enables the spectral reversal feature. the half-band decimation phase can be selected such that the half-band filter starts on the first or second sample following synchronization. this shifts the output from the half-band between the two input sample clocks. the decimation phase can be set to 0 or 1, using bit 3 of register 0x103. fixed-coefficient fir filter following the half-band filters is a 66-tap, fixed-coefficient fir filter. this filter is useful in providing extra alias protection for the decimating half-band filter. it is a simple sum-of-products fir filter with 66 filter taps and 21-bit fixed coefficients. note that this filter does not decimate. the normalized coefficients used in the implementation and the decimal equivalent value of the coefficients are listed in table 20 . the user can either select or bypass this filter, but the fir filter can be enabled only when the half-band filter is enabled. writing logic 0 to the enable fir filter bit (bit 0) in register 0x102 bypasses this fixed-coefficient filter. the filter is necessary when using the final nco with a real output; bypassing it when using other configurations results in power savings.
ad6655 rev. 0 | page 40 of 84 table 20. fir filter coefficients coefficient number normalized coefficient decimal coefficient (21-bit) c0, c65 0.0001826 383 c1, c64 0.0006824 1431 c2, c63 0.0009298 1950 c3, c62 0.0000458 96 c4, c61 ?0.0012689 ?2661 c5, c60 ?0.0008345 ?1750 c6, c59 0.0011806 2476 c7, c58 0.0011387 2388 c8, c57 ?0.0018439 ?3867 c9, c56 ?0.0024557 ?5150 c10, c55 0.0018063 3788 c11, c54 0.0035825 7513 c12, c53 ?0.0021510 ?4511 c13, c52 ?0.0056810 ?11914 c14, c51 0.0017405 3650 c15, c50 0.0078602 16484 c16, c49 ?0.0013437 ?2818 c17, c48 ?0.0110626 ?23200 c18, c47 ?0.0000229 ?48 c19, c46 0.0146618 30748 c20, c45 0.0018959 3976 c21, c44 ?0.0195594 ?41019 c22, c43 ?0.0053153 ?11147 c23, c42 0.0255623 53608 c24, c41 0.0104036 21818 c25, c40 ?0.0341468 ?71611 c26, c39 ?0.0192165 ?40300 c27, c38 0.0471258 98830 c28, c37 0.0354118 74264 c29, c36 ?0.0728111 ?152696 c30, c35 ?0.0768890 ?161248 c31, c34 0.1607208 337056 c32, c33 0.4396725 922060 synchronization the ad6655 half-band filters within a single part or across multiple parts can be synchronized using the external sync input. bit 5 and bit 6 of register 0x100 allow the half-bands to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the half-band filter to restart at the programmed decimation phase value. combined filter performance the combined response of the half-band filter and the fir filter is shown in figure 74 . the act of bandlimiting the adc data with the half-band filter ideally provides a 3 db improvement in the snr at the expense of the sample rate and available bandwidth of the output data. as a consequence of finite math, additional quantization noise is added to the system due to truncation in the nco and half-band. as a consequence of the digital filter rejection of out-of-band noise (assuming no quantization in the filters and with a white noise floor from the adc), there should be a 3.16 db improvement in the adc snr. however, the added quantization lessens improvement to about 2.66 db. 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.1 0.2 0.3 0.4 amplitude (dbc) fraction of input sample rate 06709-072 figure 74. half-band filter and fir filter composite response final nco the output of the 32-bit fine tuning nco is complex and typically centered in frequency around dc. this complex output is carried through the stages of the half-band and fir filters to provide proper antialiasing filtering. the final nco provides a means to move this complex output signal away from dc so that a real output can be provided from the ad6655. the final nco, if enabled, translates the output from dc to a frequency equal to the adc sampling frequency divided by 8 (f adc /8). this provides the user a decimated output signal centered at f adc /8 in frequency. optionally, this final nco can be bypassed, and the dc-centered i and q values can be output in an interleaved fashion.
ad6655 rev. 0 | page 41 of 84 adc overrange and gain control in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overflow indicator provides after-the-fact infor- mation on the state of the analog input that is of limited usefulness. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. in addition, because input signals can have significant slew rates, latency of this function is of major concern. highly pipelined converters can have significant latency. a good compro- mise is to use the output bits from the first stage of the adc for this function. latency for these output bits is very low, and overall resolution is not highly significant. peak input signals are typically between full scale and 6 db to 10 db below full scale. a 3-bit or 4-bit output provides adequate range and resolution for this function. using the spi port, the user can provide a threshold above which an overrange output is active. as long as the signal is below that threshold, the output should remain low. the fast detect outputs can also be programmed via the spi port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. in this mode, all 14 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. in either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). the threshold detection responds identically to positive and negative signals outside the desired range (magnitude). fast detect overview the ad6655 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control imple- mentations. each adc has four fast detect (fd) output pins that are used to output information about the current state of the adc input level. the function of these pins is programmable via the fast detect mode select bits and the fast detect enable bit in register 0x104, allowing range information to be output from several points in the internal data path. these output pins can also be set up to indicate the presence of overrange or underrange conditions, according to programmable threshold levels. table 2 1 shows the six configurations available for the fast detect pins. table 21. fast detect mode select bits settings information presented on fast detect (fd) pins of each adc 1, 2 fast detect mode select bits (register 0x104[3:1]) fd[3] fd[2] fd[1] fd[0] 000 adc fast magnitude (see table 22 ) 001 adc fast magnitude (see table 23 ) or 010 adc fast magnitude (see table 24 ) or f_lt 011 adc fast magnitude (see table 24 ) c_ut f_lt 100 or c_ut f_ut f_lt 101 or f_ut ig dg 1 the fast detect pins are fd0a/fd0b to fd3a/fd3b for the cmos mode configuration and fd0+/fd0? to fd3+/fd3? for the lvds mode configuration. 2 see the adc overrange (or) and gain switching sections for more information about or, c_ut, f_ut, f_lt, ig, and dg. adc fast magnitude when the fast detect output pins are configured to output the adc fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the adc level from an early converter stage with a latency of only two clock cycles in cmos output modes. in lvds output mode, the fast detect bits have a latency of six cycles in all fast detect modes. using the fast detect output pins in this configuration provides the earliest possible level indication information. because this information is provided early in the datapath, there is signifi- cant uncertainty in the level indicated. the nominal levels, along with the uncertainty indicated by the adc fast magnitude, are shown in table 22 . because the dco is at one-half the sample rate, the user can obtain all the fast detect information by sampling the fast detect outputs on both the rising and falling edge of dco (see figure 2 for timing information). table 22. adc fast magnitude nomimal levels with fast detect mode select bits = 000 adc fast magitude on fd[3:0] pins nominal input magnitude below fs (db) nominal input magnitude uncertainty (db) 0000 ad6655 rev. 0 | page 42 of 84 when the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins are available. in these modes, the fast detect output pins have a latency of six clock cycles, and the greater of the two input samples is output at the dco rate. table 23 shows the corresponding adc input levels when the fast detect mode select bits are set to 0b001 (that is, when the adc fast magnitude is presented on the fd[3:1] pins). table 23. adc fast magnitude nomimal levels with fast detect mode select bits = 001 adc fast magitude on fd[2:0] pins nominal input magnitude below fs (db) nominal input magnitude uncertainty (db) 000 ad6655 rev. 0 | page 43 of 84 increment gain (ig) and decrement gain (dg) the increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control. the decr ement gain indicator works in conjunction with the coarse upper threshold bits, asserting when the input magnitude is greater than the 3-bit value in the coarse upper threshold register (address 0x105). the increment gain indicator, similarly, corresponds to the fine lower threshold bits except that it is asserted only if the input magnitude is less than the value programmed in the fine lower threshold register after the dwell time elapses. the dwell time is set by the 16-bit dwell time value located at address 0x10a and address 0x10b and is set in units of adc input clock cycles ranging from 1 to 65,535. the fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the adc. this comparison is subject to the adc clock latency but allows a finer, more accurate comparison. the fine upper threshold magnitude is defined by the following equation: dbfs = 20 log( threshold magnitude /2 13 ) the decrement gain output works from the adc fast detect output pins, providing a fast indication of potential overrange conditions. the increment gain uses the comparison at the output of the adc, requiring the input magnitude to remain below an accurate, programmable level for a predefined period before signaling external circuitry to increase the gain. the operation of the increment gain output and decrement gain output is shown graphically in figure 75 . upper threshold (coarse or fine) fine lower threshold ig dg f_lt c_ut or f_ut* dwell time timer reset by rise above f_lt timer completes before signal rises above f_lt note: outputs follow the instanteous signal level and not the envelope but are guaranteed active for a minimum of 2 adc clock c ycles. *c_ut and f_ut differ only in accuracy and latency. dwell time 0 6709-073 figure 75. threshold settings fo r c_ut, f_ut, f_lt, dg, and ig
ad6655 rev. 0 | page 44 of 84 signal monitor the signal monitor block provides additional information about the signal being digitized by the adc. the signal monitor computes the rms input magnitude, the peak magnitude, and/or the number of samples by which the magnitude exceeds a particular threshold. together, these functions can be used to gain insight into the signal characteristics and to estimate the peak/average ratio or even the shape of the complementary cumulative distribution function (ccdf) curve of the input signal. this information can be used to drive an agc loop to optimize the range of the adc in the presence of real-world signals. the signal monitor result values can be obtained from the part by reading back internal registers at address 0x116 to address 0x11b, using the spi port or the signal monitor sport output. the output contents of the spi-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register (address 0x112). both adc channels must be configured for the same signal monitor mode. separate spi-accessible, 20-bit signal monitor result (smr) registers are provided for each adc channel. any combination of the signal monitor functions can also be output to the user via the serial sport interface. these outputs are enabled using the peak detector output enable, the rms magnitude output enable, and the threshold crossing output enable bits in the signal monitor sport control register (address 0x1111). for each signal monitor measurement, a programmable signal monitor period register (smpr) controls the duration of the measurement. this time period is programmed as the number of input clock cycles in a 24-bit signal monitor period register located at address 0x113, address 0x114, and address 0x115. this register can be programmed with a period from 128 samples to 16.78 (2 24 ) million samples. because the dc offset of the adc can be significantly larger than the signal of interest (affecting the results from the signal monitor), a dc correction circuit is included as part of the signal monitor block to null the dc offset before measuring the power. peak detector mode the magnitude of the input port signal is monitored over a programmable time period (determined by smpr) to give the peak value detected. this function is enabled by programming a logic 1 in the signal monitor mode bits of the signal monitor control register or by setting the peak detector output enable bit in the signal monitor sport control register. the 24-bit smpr must be programmed before activating this mode. after enabling this mode, the value in the smpr is loaded into a monitor period timer, and the countdown is started. the magnitude of the input signal is compared with the value in the internal peak level holding register (not accessible to the user), and the greater of the two is updated as the current peak level. the initial value of the peak level holding register is set to the current adc input signal magnitude. this comparison continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register (not accessible to the user), which can be read through the spi port or output through the sport serial interface. the monitor period timer is reloaded with the value in the smpr, and the countdown is restarted. in addition, the magnitude of the first input sample is updated in the peak level holding register, and the comparison and update procedure, as explained previously, continues. figure 76 is a block diagram of the peak detector logic. the smr register contains the absolute magnitude of the peak detected by the peak detector logic. power monitor holding register magnitude storage register compare a>b to memory map from memory map from input ports load clear load load to interrupt controller is count = 1? down counter power monitor period register 06709-074 figure 76. adc input peak detector block diagram rms/ms magnitude mode in this mode, the root-mean-square (rms) or mean-square (ms) magnitude of the input port signal is integrated (by adding an accumulator) over a programmable time period (determined by smpr) to give the rms or ms magnitude of the input signal. this mode is set by programming logic 0 in the signal monitor mode bits of the signal monitor control register or by setting the rms magnitude output enable bit in the signal monitor sport control register. the 24-bit smpr, representing the period over which integration is performed, must be programmed before activating this mode. after enabling the rms/ms magnitude mode, the value in the smpr is loaded into a monitor period timer, and the countdown is started immediately. each input sample is converted to floating-point format and squared. it is then converted to 11-bit, fixed-point format and added to the contents of the 24-bit accumulator. the integration continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the square root of the value in the accumulator is taken and transferred (after some formatting) to the signal monitor holding register, which can be read through the spi port or output through the sport serial port. the monitor period timer is reloaded with the value in the smpr, and the countdown is restarted.
ad6655 rev. 0 | page 45 of 84 in addition, the first input sample signal power is updated in the accumulator, and the accumulation continues with the subsequent input samples. figure 77 illustrates the rms magnitude monitoring logic. power monitor holding register accumulator from memory map from input ports load clear load is count = 1? down counter power monitor period register to memory map to interrupt controller 06709-075 figure 77. adc input rms magnitude monitoring block diagram for rms magnitude mode, the value in the signal monitor result (smr) register is a 20-bit fixed-point number. the following equation can be used to determine the rms magnitude in dbfs from the mag value in the register. note that if the signal monitor period (smp) is a power of 2, the second term in the equation becomes 0. rms magnitude = 20 log [] ? ? ? ? ? ? ? ? ? ? ? ? ? )(log 20 2 2 log10 2 smp ceil smp mag for ms magnitude mode, the value in the smr is a 20-bit fixed- point number. the following equation can be used to determine the ms magnitude in dbfs from the mag value in the register. note that if the smp is a power of 2, the second term in the equation becomes 0. ms magnitude = 10 log [] ? ? ? ? ? ? ? ? ? ? ? ? ? )(log 20 2 2 log10 2 smp ceil smp mag threshold crossing mode in the threshold crossing mode of operation, the magnitude of the input port signal is monitored over a programmable time period (given by smpr) to count the number of times it crosses a certain programmable threshold value. this mode is set by programming logic 1x (where x is a dont care bit) in the signal monitor mode bits of the signal monitor control register or by setting the threshold crossing output enable bit in the signal monitor sport control register. before activating this mode, the user needs to program the 24-bit smpr and the 13-bit upper threshold register for each individual input port. the same upper threshold register is used for both signal monitoring and gain control (see the adc overrange and gain control section). after entering this mode, the value in the smpr is loaded into a monitor period timer, and the countdown is started. the magnitude of the input signal is compared with the upper threshold register (programmed previously) on each input clock cycle. if the input signal has a magnitude greater than the upper threshold register, the internal count register is incremented by 1. the initial value of the internal count register is set to 0. this comparison and incrementing of the internal count register continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor holding register, which can be read through the spi port or output through the sport serial port. the monitor period timer is reloaded with the value in the smpr register, and the countdown is restarted. the internal count register is also cleared to a value of 0. figure 78 illustrates the threshold crossing logic. the value in the smr register is the number of samples that have a magnitude greater than the threshold register. power monitor holding register compare a>b upper threshold register compare a>b from memory map from memory map from input ports load clear load is count = 1? down counter power monitor period register b a to memory map to interrupt controller 06709-076 figure 78. adc input threshold crossing block diagram additional control bits for additional flexibility in the signal monitoring process, two control bits are provided in the signal monitor control register. they are the signal monitor enable bit and the complex power calculation mode enable bit. signal monitor enable bit the signal monitor enable bit, located in bit 0 of register 0x112, enables operation of the signal monitor block. if the signal monitor function is not needed in a particular application, this bit should be cleared to conserve power. complex power calculation mode enable bit when this bit is set, the part assumes that channel a is digitizing the i data and channel b is digitizing the q data for a complex input signal (or vice versa). in this mode, the power reported is equal to 22 qi + this result is presented in the signal monitor dc value channel a register if the signal monitor mode bits are set to 00. the signal monitor dc value channel b register continues to compute the channel b value. dc correction because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. the dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the adc is digitizing a time-varying signal with significant dc content, such as gsm.
ad6655 rev. 0 | page 46 of 84 dc correction bandwidth the dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.15 hz and 1.2 khz at 125 msps). the bandwidth is controlled by writing the 4-bit dc correction control register located at register 0x10c, bits[5:2]. the following equation can be used to compute the bandwidth value for the dc correction circuit: = ?? 2 2__ 14k clk f bwcorrdc where: k is the 4-bit value programmed in bits[5:2] of register 0x10c (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the ad6655 adc sample rate in hertz (hz). dc correction readback the current dc correction value can be read back in register 0x10d and register 0x10e for channel a and register 0x10f and register 0x110 for channel b. the dc correction value is a 14-bit value that can span the entire input range of the adc. dc correction freeze setting bit 6 of register 0x10c freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. clearing this bit restarts dc correction and adds the currently calculated value to the data. dc correction enable bits setting bit 0 of register 0x10c enables dc correction for use in the signal monitor calculations. the calculated dc correction value can be added to the output data signal path by setting bit 1 of register 0x10c. signal monitor sport output the sport is a serial interface with three output pins: the smi sclk (sport clock), smi sdfs (sport frame sync), and smi sdo (sport data output). the sport is the master and drives all three sport output pins on the chip. smi sclk the data and frame sync are driven on the positive edge of the smi sclk. the smi sclk has three possible baud rates: 1/2, 1/4, or 1/8 the adc clock rate, based on the sport controls. the smi sclk can also be gated off when not sending any data, based on the sport smi sclk sleep bit. using this bit to disable the smi sclk when it is not needed can reduce any coupling errors back into the signal path, if these prove to be a problem in the system. doing so, however, has the disadvantage of spreading the frequency content of the clock. if desired the smi sclk can be left running to ease frequency planning. smi sdfs the smi sdfs is the serial data frame sync, and it defines the start of a frame. one sport frame includes data from both datapaths. the data from datapath a is sent just after the frame sync, followed by data from datapath b. smi sdo the smi sdo is the serial data output of the block. the data is sent msb first on the next positive edge after the smi sdfs. each data output block includes one or more of rms magnitude, peak level, and threshold crossing values from each datapath in the stated order. if enabled, the data is sent, rms first, followed by peak and threshold, as shown in figure 79 . 20 cycles 16 cycles 16 cycles 20 cycles 16 cycles 16 cycles smi sdfs msb msb rms/ms ch a pk ch a pk ch b thr ch b rms/ms ch b rms/ms ch a lsb lsb thr ch a smi sdo smi sclk gated, based on control 06709-077 figure 79. signal monitor sport output ti ming (rms, peak, and threshold enabled) 20 cycles 16 cycles 20 cycles 16 cycles smi sclk smi sdfs smi sdo msb msb rms/ms ch a rms/ms ch a lsb thr ch a rms/ms ch b lsb thr ch b gated, based on control 06709-078 figure 80. signal monitor sport output timing (rms and threshold enabled)
ad6655 rev. 0 | page 47 of 84 channel/chip synchronization the ad6655 has a sync input that allows the user flexible synchronization options for synchronizing the internal blocks. the sync feature is useful for guaranteeing synchronized operation across multiple adcs. the input clock divider, nco, half-band filters, and signal monitor block can be synchronized using the sync input. each of these blocks, except for the signal monitor, can be enabled to synchronize on a single occurrence of the sync signal or on every occurrence. the sync input is internally synchronized to the sample clock. however, to ensure that there is no timing uncertainty between multiple parts, the sync input signal should be synchronized to the input clock signal. the sync input should be driven using a single-ended cmos type signal.
ad6655 rev. 0 | page 48 of 84 serial port interface (spi) the ad6655 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information, see application note an-877, interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk/dfs pin, the sdio/dcs pin, and the csb pin (see table 26 ). the sclk/dfs (serial clock) pin is used to synchronize the read and write data presented from/to the adc. the sdio/dcs (serial data input/ output) pin is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active-low control that enables or disables the read and write cycles. table 26. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active-low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 81 and table 9 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 bit and the w1 bit. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether a read command or a write command is issued. this allows the serial data input/output (sdio) pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb-first mode or in lsb-first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see application note an-877, interfacing to high speed adcs via spi at www.analog.com . hardware interface the pins described in table 26 comprise the physical interface between the user programming device and the serial port of the ad6655. the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enou gh to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in application note an-812, microcontroller- based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad6655 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to avdd or ground during device power-on, they are associated with a specific function. the digital outputs section describes the strappable functions supported on the ad6655.
ad6655 rev. 0 | page 49 of 84 configuration without the spi in applications that do not interface to the spi control registers, the sdio/dcs pin, the sclk/dfs pin, the smi sdo/oeb pin, and the smi sclk/pdwn pin serve as standalone cmos- compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. in this mode, the csb chip select should be connected to avdd, which disables the serial port interface. table 27. mode selection pin external voltage configuration avdd (default) duty cycle stabilizer enabled sdio/dcs agnd duty cycle stabilizer disabled avdd twos complement enabled sclk/dfs agnd (default) offset binary enabled avdd outputs in high impedance smi sdo/oeb agnd (default) outputs enabled avdd chip in power-down or standby smi sclk/pdwn agnd (default) normal operation spi accessible features table 28 provides a brief description of the general features that are accessible via the spi. these features are described in detail in application note an-877, interfacing to high speed adcs via spi (see www.analog.com ). the ad6655 part-specific features are described in the memory map register description section. table 28. features accessible using the spi feature name description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 06709-079 figure 81. serial port interface timing diagram
ad6655 rev. 0 | page 50 of 84 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into four sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); the adc functions registers, including setup, control, and test (address 0x08 to address 0x18); and the digital feature control registers (address 0x100 to address 0x123). the memory map register table (see table 29) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x18, the vref select register, has a hexadecimal default value of 0xc0. this means that bit 7 = 1, bit 6 = 1, and the remaining bits are 0s. this setting is the default reference selection setting. the default value uses a 2.0 v p-p reference. for more information on this function and others, see application note an-877, interfacing to high speed adcs via spi. this document details the functions controlled by register 0x00 to register 0xff. the remaining registers, from register 0x100 to register 0x123, are documented in the memory map register description section. open locations all address and bit locations that are not included in table 29 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), this address location should not be written. default values after the ad6655 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 29. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x18 and address 0x11e to address 0x123 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place when the transfer bit is set, and the bit autoclears. channel-specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 29 as local. these local registers and bits can be accessed by setting the appropriate channel a or channel b bits in register 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the value for channel a. registers and bits designated as global in table 29 affect the entire part or the channel features where independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
ad6655 rev. 0 | page 51 of 84 memory map register table all address and bit locations that are not included in table 29 are not currently supported for this device. table 29. memory map registers addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 0x00 spi port configuration (global) 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles are mirrored so that lsb- first or msb-first mode registers correctly, regardless of shift mode 0x01 chip id (global) 8-bit chip id[7:0] (ad6655 = 0x0d) (default) 0x0d default is unique chip id, different for each device; this is a read-only register 0x02 chip grade (global) open open speed grade id[4:3] 00 = 150 msps 01 = 125 msps 10 = 105 msps 11 = 80 msps open open open open speed grade id used to differentiate devices; this is a read-only register channel index and transfer registers 0x05 channel index open open open open open open data channel b (default) data channel a (default) 0x03 bits are set to determine which device on chip receives the next write command; applies to local registers 0xff transfer open open open ope n open open open transfer 0x00 synchronously transfers data from the master shift register to the slave adc function registers 0x08 power modes open open external power- down pin function (global) 0 = pdwn 1 = stndby open open open internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation 0x00 determines various generic modes of chip operation 0x09 global clock (global) open open open ope n open open open duty cycle stabilize (default) 0x01 0x0b clock divide (global) open open open open open clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 clock divide values other than 000 automatically activate duty cycle stabilization
ad6655 rev. 0 | page 52 of 84 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x0d test mode (local) open open reset pn long sequence reset pn short sequence open output test mode 000 = off (default) 001 = midscale short 010 = positive fs 011 = negative fs 100 = alternating checkerboard 101 = pn long sequence 110 = pn short sequence 111 = one/zero word toggle 0x00 when enabled, the test data is placed on the output pins in place of adc output data 0x10 offset adjust (local) open open offset adjust in lsbs from +31 to -32 (twos complement format) 0x00 0x14 output mode drive strength 0 v to 3.3 v cmos or ansi lvds; 1 v to 1.8 v cmos or reduced lvds (global) output type 0 = cmos 1 = lvds (global) interleaved cmos (global) output enable bar (local) open output invert (local) 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) 0x00 configures the outputs and the format of the data 0x16 clock phase control (global) invert dco clock open open open open in put clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 allows selection of clock delays into the input divider 0x17 dco output delay (global) open open open dco clock delay (delay = 2500 ps register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps 11110 = 2419 ps 11111 = 2500 ps 0x00 0x18 vref select (global) reference voltage selection 00 = 1.25 v p-p 01 = 1.5 v p-p 10 = 1.75 v p-p 11 = 2.0 v p-p (default) open open open open open open 0xc0 digital feature control registers 0x100 sync control (global) signal monitor sync enable half-band next sync only half-band sync enable nco32 next sync only nco32 sync enable clock divider next sync only clock divider sync enable master sync enable 0x00 0x101 f s /8 output mix control (global) open open f s /8 start state open open f s /8 next sync only f s /8 sync enable 0x00 0x102 fir filter and output mode control (global) open open open open fir gain 0 = gain of 2 1 = gain of 1 f s /8 output mix disable complex output enable fir filter enable 0x00 0x103 digital filter control (global) open open open open half-band decimation phase spectral reversal high-pass/ low-pass select open 0x01
ad6655 rev. 0 | page 53 of 84 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x104 fast detect control (local) open open open open fast de tect mode select[2:0] fast detect enable 0x00 0x105 coarse upper threshold (local) open open open open open coarse upper thre shold[2:0] 0x00 0x106 fine upper threshold register 0 (local) fine upper threshold[7:0] 0x00 0x107 fine upper threshold register 1 (local) open open open fine upper threshold[12:8] 0x00 0x108 fine lower threshold register 0 (local) fine lower thresh old[7:0] 0x00 0x109 fine lower threshold register 1 (local) open open open fine lower threshold[12:8] 0x00 0x10a increase gain dwell time register 0 (local) increase gain dwell time[7:0] 0x00 in adc clock cycles 0x10b increase gain dwell time register 1 (local) increase gain dwel l time[15:8] 0x00 in adc clock cycles 0x10c signal monitor dc correction control (global) open dc correction freeze dc correction bandwidth(k:[3:0]) dc correction for signal path enable dc correction for signal monitor enable 0x00 0x10d signal monitor dc value channel a register 0 (global) dc value channel a[7:0] read only 0x10e signal monitor dc value channel a register 1 (global) open open dc value channe l a[13:8] read only 0x10f signal monitor dc value channel b register 0 (global) dc value channel b[7:0] read only 0x110 signal monitor dc value channel b register 1 (global) open open dc value channe l b[13:8] read only 0x111 signal monitor sport control (global) open rms magnitude output enable peak detector output enable threshold crossing output enable sport smi sclk divide 00 = undefined 01 = divide by 2 10 = divide by 4 11 = divide by 8 sport smi sclk sleep signal monitor sport output enable 0x04
ad6655 rev. 0 | page 54 of 84 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x112 signal monitor control (global) complex power calculation mode enable open open open signal monitor rms/ms select 0 = rms 1 = ms signal monitor mode 00 = rms/ms magnitude 01 = peak detector 10 = threshold crossing 11 = threshold crossing signal monitor enable 0x00 0x113 signal monitor period register 0 (global) signal monitor period[7:0] 0x80 in adc clock cycles 0x114 signal monitor period register 1 (global) signal monitor period[15:8] 0x00 i in adc clock cycles 0x115 signal monitor period register 2 (global) signal monitor period[23:16] 0x00 in adc clock cycles 0x116 signal monitor result channel a register 0 (global) signal monitor result channel a[7:0] read only 0x117 signal monitor result channel a register 1 (global) signal monitor result channel a[15:8] read only 0x118 signal monitor result channel a register 2 (global) open open open open signal monitor result channel a[19:16] read only 0x119 signal monitor result channel b register 0 (global) signal monitor result cha nnel b[7:0] read only 0x11a signal monitor result channel b register 1 (global) signal monitor result cha nnel b[15:8] read only 0x11b signal monitor result channel b register 2 (global) open open open open signal monitor result channel b[19:16] read only 0x11d nco control (global) open open open open open nco32 phase dither enable nco32 amplitude dither enable nco32 enable 0x00 0x11e nco frequency 0 nco frequency value[7:0] 0x00 0x11f nco frequency 1 nco frequency value[15:8] 0x00 0x120 nco frequency 2 nco frequency value[23:16] 0x00
ad6655 rev. 0 | page 55 of 84 addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 0x121 nco frequency 3 nco frequency value[31:24] 0x00 0x122 nco phase offset 0 nco phase value[7:0] 0x00 0x123 nco phase offset 1 nco phase value[15:8] 0x00 memory map register description for more information on functions controlled in register 0x00 to register 0xff, see application note an-877, interfacing to high speed adcs via spi , at www.analog.com . sync control (register 0x100) bit 7signal monitor sync enable bit 7 enables the sync pulse from the external sync input to the signal monitor block. the sync signal is passed when bit 7 and bit 0 are high. this is continuous sync mode. bit 6half-band next sync only if the master sync enable bit (register 0x100, bit 0) and the half- band sync enable bit (register 0x100, bit 5) are high, bit 6 allows the nco32 to synchronize following the first sync pulse it receives and ignore the rest. if bit 6 is set, bit 5 of register 0x100 resets after this sync occurs. bit 5half-band sync enable bit 5 gates the sync pulse to the half-band filter. when bit 5 is set high, the sync signal causes the half-band to resynchro- nize, starting at the half-band decimation phase selected in register 0x103, bit 3. this sync is active only when the master sync enable bit (register 0x100, bit 0) is high. this is continuous sync mode. bit 4nco32 next sync only if the master sync enable bit (register 0x100, bit 0) and the nco32 sync enable bit (register 0x100, bit 3) are high, bit 4 allows the nco32 to synchronize following the first sync pulse it receives and ignore the rest. bit 3 of register 0x100 resets after a sync occurs if bit 4 is set. bit 3nco32 sync enable bit 3 gates the sync pulse to the 32-bit nco. when this bit is set high, the sync signal causes the nco to resynchronize, starting at the nco phase offset value. this sync is active only when the master sync enable bit (register 0x100, bit 0) is high. this is continuous sync mode. bit 2clock divider next sync only if the master sync enable bit (register 0x100, bit 0) and the clock divider sync enable bit (register 0x100, bit 1) are high, bit 2 allows the clock divider to synchronize following the first sync pulse it receives and ignores the rest. bit 1 of register 0x100 resets after it synchronizes. bit 1clock divider sync enable bit 1 gates the sync pulse to the clock divider. the sync signal is passed when bit 1 and bit 0 are high. this is continuous sync mode. bit 0master sync enable bit 0 must be high to enable any of the sync functions. f s /8 output mix control (register 0x101) bits[7:6]reserved bits[5:4]f s /8 start state bit 5 and bit 4 set the starting phase of the f s /8 output mix. bits[3:2]reserved bit 1f s /8 next sync only if the master sync enable bit (register 0x100, bit 0) and the f s /8 sync enable bit (register 0x101, bit 0) are high, bit 1 allows the f s /8 output mix to synchronize following the first sync pulse it receives and ignore the rest. bit 0 of register 0x100 resets after it synchronizes. bit 0f s /8 sync enable bit 0 gates the sync pulse to the f s /8 output mix. this sync is active only when the master sync enable bit (register 0x100, bit 0) is high. this is continuous sync mode. fir filter and output mode control (register 0x102) bits[7:4]reserved bit 3fir gain when bit 3 is set high, the fir filter path, if enabled, has a gain of 1. when bit 3 set low, the fir filter path has a gain of 2. bit 2f s /8 output mix disable bit 2 disables the f s /8 output mix when enabled. bit 2 should be set along with bit 1 to enable complex output mode. bit 1complex output mode enable setting bit 1 high enables complex output mode. bit 0fir filter enable when set high, bit 0 enables the fir filter. when bit 0 is cleared, the fir filter is bypassed and shut down for power savings.
ad6655 rev. 0 | page 56 of 84 digital filter control (register 0x103) bits[7:4]reserved bit 3half-band decimation phase when set high, bit 3 uses the alternate phase of the decimating half-band filter. bit 2spectral reversal bit 2 enables the spectral reversal feature of the half-band filter. bit 1high-pass/low-pass select bit 1 enables the high-pass mode of the half-band filter when set high. setting this bit low enables the low-pass mode (default). bit 0reserved bit 0 reads back as a 1. fast detect control (register 0x104) bits[7:4]reserved bits[3:1]fast detect mode select bits[3:1] set the mode of the fast detect output bits according to table 29 . bit 0fast detect enable bit 0 is used to enable the fast detect output pins. when the fd outputs are disabled, the outputs go into a high impedance state. in lvds mode when the outputs are interleaved, the outputs go high-z only if both channels are turned off (power-down/ standby/output disabled). if only one channel is turned off (power-down/standby/output disabled), the fast detect outputs repeat the data of the active channel. coarse upper threshold (register 0x105) bits[7:3]reserved bits[2:0]coarse upper threshold these bits set the level required to assert the coarse upper threshold indication (see tabl e 25 ). fine upper threshold (registe r 0x106 and register 0x107) register 0x107, bits[7:5]reserved register 0x107, bits[4:0]fine upper threshold bits[12:8] register 0x106, bits[7:0]fine upper threshold bits[7:0] these registers provide a fine upper limit threshold. the 13-bit value is compared to the 13-bit magnitude from the adc block. if the adc magnitude exceeds this threshold value, the f_ut indicator is set. fine lower threshold (registe r 0x108 and register 0x109) register 0x109, bits[7:5]reserved register 0x109, bits[4:0]fine lower threshold bits[12:8] register 0x108, bits[7:0]fine lower threshold bits[7:0] these registers provide a fine lower limit threshold. this 13-bit value is compared with the 13-bit magnitude from the adc block. if the adc magnitude is less than this threshold value, the f_lt indicator is set. increase gain dwell time (register 0x10a and register 0x10b) register 0x10b, bits[7:0]increase gain dwell time bits[15:8] register 0x10a, bits[7:0]increase gain dwell time bits[7:0] these register values set the minimum time in adc sample clock cycles (after clock divider) that a signal needs to stay below the fine lower threshold limit before the f_lt and ig are asserted high. signal monitor dc correction control (register 0x10c) bit 7reserved bit 6dc correction freeze when bit 6 is set high, the dc correction is no longer updated to the signal monitor block, which holds the last dc value calculated. bits[5:2]dc correction bandwidth bits[5:2] set the averaging time of the signal monitor dc correction function. this 4-bit word sets the bandwidth of the correction block, according to the following equation: = ?? 2 2__ 14k clk f bwcorrdc where: k is the 4-bit value programmed in bits[5:2] of register 0x10c (values between 0 and 13 are valid for k; programming 14 or 15 provides the same result as programming 13). f clk is the ad6655 adc sample rate in hertz (hz). bit 1dc correction for signal path enable setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path. bit 0dc correction for signal monitor enable this bit enables the dc correction function in the signal monitor block. the dc correction is an averaging function that can be used by the signal monitor to remove dc offset in the signal. removing this dc from the measurement allows a more accurate power reading. signal monitor dc value channel a (register 0x10d and register 0x10e) register 0x10e, bits[7:6]reserved register 0x10e, bits[5:0]dc value channel a[13:8] register 0x10d, bits[7:0]dc value channel a[7:0] these read-only registers hold the latest dc offset value computed by the signal monitor for channel a.
ad6655 rev. 0 | page 57 of 84 signal monitor dc value channel b (register 0x10f and register 0x110) register 0x110, bits[7:6]reserved register 0x110, bits[5:0]channel b dc value bits[13:8] register 0x10f, bits[7:0]channel b dc value bits [7:0] these read-only registers hold the latest dc offset value computed by the signal monitor for channel b. signal monitor sport co ntrol (register 0x111) bit 7reserved bit 6rms/ms magnitude output enable bit 6 enables the 20-bit rms or ms magnitude measurement as output on the sport. bit 5peak detector output enable bit 5 enables the 13-bit peak measurement as output on the sport. bit 4threshold crossing output enable bit 4 enables the 13-bit threshold measurement as output on the sport. bits[3:2]sport smi sclk divide the values of these bits set the sport smi sclk divide ratio from the input clock. a value of 0x01 sets divide by 2 (default), a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8. bit 1sport smi sclk sleep setting bit 1 high causes the smi sclk to remain low when the signal monitor block has no data to transfer. bit 0signal monitor sport output enable when set, bit 0 enables the signal monitor sport output to begin shifting out the result data from the signal monitor block. signal monitor control (register 0x112) bit 7complex power calculation mode enable this mode assumes i data is present on one channel and q data is present on the alternate channel. the result reported is the complex power measured as 22 qi + bits[6:4]reserved bit 3signal monitor rms/ms select setting bit 3 low selects rms power measurement mode. setting bit 3 high selects ms power measurement mode. bits[2:1]signal monitor mode bit 2 and bit 1 set the mode of the signal monitor for data output to registers at address 0x116 through address 0x11b. setting these bits to 0x00 selects rms/ms magnitude output, setting these bits to 0x01 selects peak detector output, and setting 0x10 or 0x11 selects threshold crossing output. bit 0signal monitor enable setting bit 0 high enables the signal monitor block. signal monitor period (register 0x113 to register 0x115) register 0x115 bits[7:0]signal monitor period[23:16] register 0x114 bits[7:0]signal monitor period[15:8] register 0x113 bits[7:0]signal monitor period[7:0] this 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. the minimum value for this register is 128 cycles (programmed values less than 128 revert to 128). signal monitor result ch annel a (register 0x116 to register 0x118) register 0x118, bits[7:4]reserved register 0x118, bits[3:0]signal monitor result channel a[19:16] register 0x117, bits[7:0]signal monitor result channel a[15:8] register 0x116, bits[7:0]signal monitor result channel a[7:0] this 20-bit value contains the power value calculated by the signal monitor block for channel a. the content is dependent on the settings in register 0x112, bits[2:1]. signal monitor result channel b (register 0x119 to register 0x11b) register 0x11b, bits[7:4]reserved register 0x11b, bits[3:0]signal monitor result channel b[19:16] register 0x11a, bits[7:0]signal monitor result channel b[15:8] register 0x119, bits[7:0]signal monitor result channel b[7:0] this 20-bit value contains the power value calculated by the signal monitor block for channel b. the content is dependent on the settings in register 0x112, bits[2:1]. nco control (register 0x11d) bits[7:3]reserved bit 2nco32 phase dither enable when bit 2 is set, phase dither in the nco is enabled. when bit 2 is cleared, phase dither is disabled. bit 1nco32 amplitude dither enable when bit 1 is set, amplitude dither in the nco is enabled. when bit 1 is cleared, amplitude dither is disabled.
ad6655 rev. 0 | page 58 of 84 nco phase offset (register 0x122 and register 0x123) bit 0nco32 enable register 0x122, bits[7:0]nco phase value[7:0] when bit 0 is set, this bit enables the 32-bit nco operating at the frequency programmed into the nco frequency register. when bit 0 is cleared, the nco is bypassed and shuts down for power savings. register 0x123, bits[7:0]nco phase value[15:8] the 16-bit value programmed into the nco phase value register is loaded into the nco block each time the nco is started or when an nco sync signal is received. this process allows the nco to be started with a known nonzero phase. nco frequency (register 0x11e to register 0x121) register 0x11e, bits[7:0]nco frequency value[7:0] register 0x11f, bits[7:0]nco frequency value[15:8] use the following equation to calculate the nco phase offset value: register 0x120, bits[7:0]nco frequency value[23:16] nco _ phase = 2 16 phase /360 register 0x121, bits[7:0]nco frequency value[31:24] where: nco_phase is a decimal number equal to the 16-bit binary number to be programmed at register 0x122 and register 0x123. phase is the desired nco phase in degrees. this 32-bit value is used to program the nco tuning frequency. the frequency value to be programmed is given by the following equation: clk clk f ffmod nco_freq ),( 2 32 = where: nco_freq is a 32-bit twos complement number representing the nco frequency register. f is the desired carrier frequency in hertz (hz). f clk is the ad6655 adc clock rate in hertz (hz).
ad6655 rev. 0 | page 59 of 84 applications information design guidelines before starting system-level design and layout of the ad6655, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad6655, it is recommended that two separate 1.8 v supplies be used: one supply should be used for analog (avdd) and digital (dvdd), and a separate supply should be used for the digital outputs (drvdd). the avdd and dvdd supplies, while derived from the same source, should be isolated with a ferrite bead or filter choke and separate decoupling capacitors. the designer can employ several different decoupling capacitors to cover both high and low frequencies. these capacitors should be located close to the point of entry at the pc board level and close to the pins of the part with minimal trace length. a single pcb ground plane should be sufficient when using the ad6655. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. f s /2 spurious because the ad6655 output data rate is at one-half the sampling frequency, there is significant f s /2 energy in the outputs of the part. if this f s /2 spur falls in band, care must be taken to ensure that this f s /2 energy does not couple into either the clock circuit or the analog inputs of the ad6655. when f s /2 energy is coupled in this fashion, it appears as a spurious tone reflected around f s /4, 3f s /4, 5f s /4, and so on. for example, in a 125 msps sampling application with a 90 mhz single-tone analog input, this energy generates a tone at 97.5 mhz. in this example, the center of the nyquist zone is 93.75 mhz; therefore, the 90 mhz input signal is 3.75 mhz from the center of the nyquist zone. as a result, the f s /2 spurious tone appears at 97.5 mhz, or 3.75 mhz above the center of the nyquist zone. these frequencies are then tuned by the ncos before being output by the ad6655. depending on the relationship of the if frequency to the center of the nyquist zone, this spurious tone may or may not exist in the ad6655 output band. some residual f s /2 energy is present in the ad6655, and the level of this spur is typically below the level of the harmonics at clock rates of 125 msps and below. figure 82 shows a plot of the f s /2 spur level vs. analog input frequency for the ad6655-125. at sampling rates above 125 msps, the f s /2 spur level increases and is at a higher level than the worst harmonic, as shown in figure 83 , which shows the ad6655-150 f s /2 levels. for the specifications provided in table 2 , the f s /2 spur, if in band, is excluded from the snr values. it is treated as a harmonic, in terms of snr. the f s /2 level is included in the sfdr and worst other specifications. ? 60 ?70 ?80 ?90 ?100 ?110 ?120 0 50 100 150 200 250 350300 400 450 500 06709-083 input frequency (mhz) ?sfdr sfdr and f s /2 spur (dbfs) f s /2 spur figure 82. ad6655-125 sfdr and f s /2 spurious level vs. input frequency (f in ) with drvdd = 1.8 v parallel cmos output mode ? 60 ?70 ?80 ?90 ?100 ?110 ?120 0 50 100 150 200 250 350300 400 450 500 06709-084 analog input frequency (mhz) ?sfdr sfdr and f s /2 spur (dbfs) f s /2 spur figure 83. ad6655-150 sfdr and f s /2 spurious level vs. input frequency (f in ) with drvdd = 1.8 v parallel cmos output mode operating the part with a 1.8 v drvdd voltage rather than a 3.3 v drvdd lowers the f s /2 spur. in addition, using lvds, cmos interleaved, or cmos iq output modes also reduces the f s /2 spurious level. lvds operation the ad6655 defaults to cmos output mode on power-up. if lvds operation is desired, this mode must be programmed using the spi configuration registers after power-up. when the ad6655 powers up in cmos mode with lvds termination resistors (100 ) on the outputs, the drvdd current can be higher than the typical value until the part is placed in lvds mode. this additional drvdd current does not cause damage to the ad6655, but it should be taken into account when consid- ering the maximum drvdd current for the part.
ad6655 rev. 0 | page 60 of 84 to avoid this additional drvdd current, the ad6655 outputs can be disabled at power-up by taking the oeb pin high. after the part is placed into lvds mode via the spi port, the oeb pin can be taken low to enable the outputs. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb should mate to the ad6655 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about packaging and pcb layout of chip scale packages, refer to application note an-772, a design and manufacturing guide for the lead frame chip scale package (lfcsp) (see www.analog.com ). cml the cml pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 48 . rbias the ad6655 requires that a 10 k resistor be placed between the rbias pin and ground. this resistor sets the master current reference of the adc core and should have at least a 1% tolerance. reference decoupling the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad6655 to keep these signals from transitioning at the converter inputs during critical sampling periods.
ad6655 rev. 0 | page 61 of 84 evaluation board the ad6655 evaluation board provides all of the support circuitry required to operate the adc in its various modes and configura- tions. the converter can be driven differentially through a double balun configuration (default) or optionally through the ad8352 differential driver. the adc can also be driven in a single-ended fashion. separate power pins are provided to isolate the dut from the ad8352 drive circuitry. each input configuration can be selected by proper connection of various components (see figure 85 to figure 94 ). figure 84 shows the typical bench characterization setup used to evaluate the ac performance of the ad6655. it is critical that the signal sources used for the analog input and clock have very low phase noise (<<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 85 to figure 102 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board comes with a wall-mountable switching power supply that provides a 6 v, 2 a maximum output. connect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the output of the supply is a 2.1 mm inner diameter circular jack that connects to the pcb at j16. once on the pc board, the 6 v supply is fused and conditioned before connection to six low dropout linear regulators that supply the proper bias to each of the various sections on the board. external supplies can be used to operate the evaluation board by removing l1, l3, l4, and l13 to disconnect the voltage regulators supplied from the switching power supply. this enables the user to individually bias each section of the board. use p3 and p4 to connect a different supply for each section. at least one 1.8 v supply is needed with a 1 a current capability for avdd and dvdd; a separate 1.8 v to 3.3 v supply is recom- mended for drvdd. to operate the evaluation board using the ad8352 option, a separate 5.0 v supply (amp vdd) with a 1 a current capability is needed. to operate the evaluation board using the alternate spi options, a separate 3.3 v analog supply (vs) is needed, in addition to the other supplies. the 3.3 v supply (vs) should have a 1 a current capability, as well. solder jumper sj35 allows the user to separate avdd and dvdd, if desired. input signals when connecting the clock and analog source, use clean signal generators with low phase noise, such as the rohde & schwarz sma100a signal generators or the equivalent. use 1 m long, shielded, rg-58, 50 coaxial cable for making connections to the evaluation board. enter the desired frequency and amplitude for the adc. the ad6655 evaluation board from analog devices, inc., can accept a ~2.8 v p-p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recom- mended that a multipole, narrow-band, band-pass filter with 50 terminations be used. band-pass filters of this type are available from tte, allen avionics, and k&l microwave, inc. connect the filter directly to the evaluation board, if possible. output signals the parallel cmos outputs interface directly with the analog devices standard adc data capture board (hsc-adc-evalcz). for more information on the adc data capture boards and their optional settings, visit www.analog.com/fifo . 0 6709-108 usb connection ad6655 evaluation board 14-bit parallel cmos 14-bit parallel cmos hsc-adc-evalcz fpga based data capture board pc running visual analog and spi controller software 1.8v ?+ ?+ avdd in vs drvdd in gnd gnd ?+ 5.0v gnd amp vdd 3.3v 6v dc 2a max wall outlet 100v to 240v ac 47hz to 63hz switching power supply ?+ gnd 3.3v vcp ?+ gnd 3.3v spi spi rohde & schwarz, sma100a, 2v p-p signal synthesizer clk rohde & schwarz, sma100a, 2v p-p signal synthesizer ainb band-pass filter rohde & schwarz, sma100a, 2v p-p signal synthesizer aina band-pass filter figure 84. evaluation board connection
ad6655 rev. 0 | page 62 of 84 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad6655 evaluation board. power connect the switching power supply that is provided in the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p500. vin the evaluation board is set up for a double balun configuration analog input with optimum 50 impedance matching from 70 mhz to 200 mhz. for more bandwidth response, the differ- ential capacitor across the analog inputs can be changed or removed (see table 14 ). the common mode of the analog inputs is developed from the center tap of the transformer via the cml pin of the adc (see the analog input considerations section). vref vref is set to 1.0 v by tying the sense pin to ground by adding a jumper on header j5 (pin 1 to pin 2). this causes the adc to operate in 2.0 v p-p full-scale range. to place the adc in 1.0 v p-p mode (vref = 0.5 v), a jumper should be placed on header j4. a separate external reference option is also included on the evalua- tion board. to use an external reference, connect j6 (pin 1 to pin 2) and provide an external reference at tp5. proper use of the vref options is detailed in the volt age reference section. rbias rbias requires a 10 k resistor (r503) to ground and is used to set the adc core bias current. clock the default clock input circuitry is derived from a simple balun- coupled circuit using a high bandwidth 1:1 impedance ratio balun (t5) that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle single- ended sine wave inputs. the transformer converts the single-ended input to a differential signal that is clipped before entering the adc clock inputs. when the ad6655 input clock divider is utilized, clock frequencies up to 625 mhz can be input into the evaluation board through connector s5. pdwn to enable the power-down feature, connect j7, shorting the pdwn pin to avdd. csb the csb pin is internally pulled up, setting the chip into external pin mode, to ignore the sdio and sclk information. to connect the control of the csb pin to the spi circuitry on the evaluation board, connect j21, pin 1 to j21, pin 2. sclk/dfs if the spi port is in external pin mode, the sclk/dfs pin sets the data format of the outputs. if the pin is left floating, the pin is inter- nally pulled down, setting the default data format condition to offset binary. connecting j2, pin 1 to j2, pin 2 sets the format to twos complement. if the spi port is in serial pin mode, connecting j2, pin 2 to j2, pin 3 connects the sclk pin to the on-board spi circuitry (see the serial port interface (spi) section). sdio/dcs if the spi port is in external pin mode, the sdio/dcs pin sets the duty cycle stabilizer. if the pin is left floating, the pin is internally pulled up, setting the default condition to dcs enabled. to disable the dcs, connect j1, pin 1 to j1, pin 2. if the spi port is in serial pin mode, connecting j1, pin 2 to j1, pin 3 connects the sdio pin to the on-board spi circuitry (see the serial port interface (spi) section). alternative clock configurations two alternate clocking options are provided on the ad6655 evaluation board. the first option is to use an on-board crystal oscillator (y1) to provide the clock input to the part. to enable this crystal, resistor r8 (0 ) and resistor r85 (10 k) should be installed, and resistor r82 and resistor r30 should be removed. a second clock option is to use a differential lvpecl clock to drive the adc input using the ad9516 (u2). when using this drive option, the ad9516 charge pump filter components need to be populated (see figure 89 ). consult the ad9516 data sheet for more information. to configure the clock input from s5 to drive the ad9516 reference input instead of directly driving the adc, the following components need to be added, removed, and/or changed. 1. remove r32, r33, r99, and r101 in the default clock path. 2. populate c78 and c79 with 0.001 f capacitors and r78 and r79 with 0 resistors in the clock path. in addition, unused ad9516 outputs (one lvds and one lvpecl) are routed to optional connector s8 through connector s11 on the evaluation board.
ad6655 rev. 0 | page 63 of 84 alternative analog input drive configuration this section provides a brief description of the alternative analog input drive configuration using the ad8352 . when using this particular drive option, some additional components need to be populated. for more details on the ad8352 differential driver, including how it works and its optional pin settings, consult the ad8352 data sheet. to configure the analog input to drive the ad8352 instead of the default transformer option, the following components need to be added, removed, and/or changed for channel a. for channel b, the corresponding components should be changed. 1. remove c1, c17, c18, and c117 in the default analog input path. 2. populate c8 and c9 with 0.1 f capacitors in the analog input path. to drive the ad8352 in the differential input mode, populate the t10 transformer; the r1, r37, r39, r126, and r127 resistors; and the c10, c11, and c125 capacitors. 3. populate the optional amplifier output path with the desired components including an optional low-pass filter. install 0 resistors, r44 and r48. r43 and r47 should be increased (typically to 100 ) to increase to 200 the output impedance seen by the ad8352 .
ad6655 rev. 0 | page 64 of 84 schematics 06709-200 ba ind060 3 12 1 2 3 6 5 4 ind060 3 12 9 12 enb 15 67 4 3 2 8 13 vcm 14 vin 5 vip 16 von 10 vop 11 ad835 2 1 vcc gnd gnd gnd vcc rgn rdn rgp rdp 1 2 5 4 1 2 3 ps f 5 4 1 2 3 p s f 1 1 5 4 1 2 3 ps f ind060 3 12 1 2 ind060 3 12 dnp dnp dnp optional amplifier input path default amplifier input path transformer/amp channel a ain+ ain- dnp dnp dnp l16 180nh r31 0ohm c16 0.001 u r5 57.6 ohm r1 57.6 ohm r28 57.6 ohm r126 4.12k r27 33 ohm r26 33 ohm r41 10k ohm r4 0 10k ohm s2 amp+ a l17 180nh vin-a avdd r50 0ohm vin+a amp+ a amp-a ina+ ina- ina - ina+ etc1-1-1 3 t10 c125 .3pf r127 100 ohm r121 res040 2 0ohm r4 0ohm r48 0ohm r49 0ohm r47 33 ohm r43 33 ohm r42 0ohm r44 0ohm r110 0ohm r2 0ohm r120 0ohm r39 0ohm r38 dn p r37 0ohm r36 dn p r54 0ohm r35 24.9 ohm r29 24.9 ohm tp15 tp14 c27 10u c23 0.1u c22 0.1u etc1-1-13 t2 etc1-1-13 t1 cml cml avdd amp-a ampvd d c9 0.1u c4 18p f c139 12p f c5 4.7p f c12 0.001 u c3 0.1u c1 0.1u c8 0.1u c10 0.1u c11 0.1u c47 0.1u c117 0.1u c17 0.1u c18 0.1u c2 0.1u s1 z1 l14 120nh adt1_1wt t7 l15 120nh ampvd d w1 ampvd d figure 85. evaluation board schematic, channel a analog inputs
ad6655 rev. 0 | page 65 of 84 06709-201 ba enb vcm vin vip von vop ad835 2 vcc gnd gnd gnd vcc rgn rdn rgp rdp ps f ind060 3 ind060 3 ind060 3 ind060 3 ps f ps f dnp dnp dnp dnp dnp optional amplifier input path default amp lifier input path ain+ ain- dnp r133 dn p r72 57.6 oh m r52 57.6 oh m r51 57.6 oh m r128 4.12k r73 33 oh m r74 33 oh m r70 33 oh m r71 33 oh m r53 10k oh m ampvd d r131 10k oh m r135 24.9 oh m r129 100 oh m r69 0ohm r67 0ohm r123 res0402 0ohm r122 res0402 0ohm r111 0ohm r94 0ohm r95 0ohm r96 0ohm r81 0ohm r80 0ohm r55 0ohm r6 0ohm r68 dn p r134 24.9 oh m r132 0ohm r66 0ohm 3 2 1 4 5 etc1-1-1 3 t4 4 5 6 3 2 1 adt1_1w t t8 3 2 1 4 5 etc1-1-1 3 t3 c51 0.1u c28 0.1u inb - inb+ cml amp-b amp+b cml vin- b avdd avdd amp-b amp+b ampvdd inb- inb+ c19 18pf c29 12pf c84 4.7pf c128 .3pf c46 0.001 u c140 0.001 u c38 0.1u c30 0.1u c31 0.1u c82 0.1u c83 0.1u c24 0.1u c7 0.1u c39 0.1u c6 0.1u 2 1 s3 2 1 s4 1 tp16 1 tp17 12 l19 120nh 12 l21 180nh 12 l20 180nh 12 l18 120nh 3 2 1 4 5 etc1-1-1 3 t11 9 12 67 15 4 1 3 2 8 13 5 16 14 10 11 z2 w2 c62 10u c61 0.1u c60 0.1u ampvd d vin+b figure 86. evaluation board schematic, channel b analog inputs
ad6655 rev. 0 | page 66 of 84 06709-202 ps f en c en c \ vs c145 0.1u c20 0.1u r85 10kohm r8 0ohm 21 tp2 r84 24.9ohm r79 0ohm r34 dnp r101 0ohm r3 0ohm r7 57.6ohm r90 0ohm r30 57.6ohm r32 0ohm r33 0ohm r99 0ohm r78 0ohm r82 10kohm altclk - c64 0.001u c94 0.001u 3 2 1 4 5 etc1-1-1 3 t5 c79 0.001u opt_clk- clk- clk+ opt_clk+ opt_clk+ c77 0.001u c78 0.001u c63 0.001u c56 0.1u c21 0.1u 2 1 sma200u p s6 2 1 sma200u p s5 4 5 6 3 2 1 adt1_1w t t9 opt_clk- altclk + r83 24.9ohm figure 87. evaluation board schematic, dut clock input
ad6655 rev. 0 | page 67 of 84 06709-203 test test test bypass_ld o clk cp cp_rse t gnd_es d gnd_out89_di v gnd_ref ld lf nc1 nc2 nc3 nc4 out0 out1 out 2 out 3 out4 out5 out 6 out 7 out 8 out 9 refi n refmo n ref_se l rset_cloc k sclk sdio sdo statu s vcp vs_clk_dis t vs_out01_di v vs_out01_dr v vs_out23_di v vs_out23_dr v vs_out45_di v vs_out45_dr v vs_out67_ 1 vs_out67_ 2 vs_out89_ 1 vs_out89_ 2 vs_pll_ 1 vs_pll_ 2 vs_prescale r vs_re f vs_vc o clkb csb out0 b out1 b out2 b out3 b out4 b out5 b out6 b out7 b out8 b out9 b pdb refin b reset b sync b ad9516_64lfcs p pad 2 ad9516 clk in lvds output lvpecl output to adc lvpecl 1 s7 vcxo_clk - r89 49.9 ohm r12 4.12k r9 100 ohm r75 100 ohm 1 tp8 2 1 s11 out6 p out6 n 10 13 5 62 44 37 59 3 9 15 18 19 20 56 53 43 40 25 28 48 46 33 35 2 7 58 22 21 6 4 12 51 54 38 41 30 27 49 50 31 32 61 60 57 11 14 17 55 52 42 39 26 29 47 45 34 36 24 63 23 8 1 16 64 u2 200 r91 200 r86 r11 5.1k 200 r88 200 r92 r125 res040 2 0ohm r124 res040 2 0ohm r10 0ohm c104 0.1u c101 0.1u c98 0.1u c99 0.1u c96 0.1u c97 0.1u c100 0.1u sync vcp vs_out_d r vcxo_clk + 1 tp18 ld 1 tp19 c80 18p f c141 0.001 u c86 0.1u c85 0.1u c87 0.1u c88 0.1u c143 0.1u c142 0.1u 2 1 s10 2 1 s9 2 1 s8 1 tp20 opt_clk + sclk vs sync b reset b opt_clk - pdb csb_ 2 vs vs vs vs vs vs_out_d r vs_out_d r vs vs_out_d r vcp sdo sdi ref_se l lf agnd agnd agnd cp bypass_ld o statu s refmo n altclk - altclk + figure 88. evaluation board schematic, optional ad9516 clock circuit
ad6655 rev. 0 | page 68 of 84 06709-204 a1 gnd a2 y1 vcc y2 out2 out1 vcc gnd out_disable freq_ctrl_v vs-500 ac val val val val val charge pump filter sync vs vs c144 sel c92 sel c89 sel r93 r87 24.9 oh m r98 r136 r137 r97 r117 res0402 0ohm r116 res0402 0ohm r108 res0402 10k oh m r109 res0402 10k oh m r107 res0402 10k oh m r106 res0402 10k oh m r139 res0402 0ohm r114 res0402 0ohm r105 res0402 10k oh m r103 res0402 10k oh m r102 res0402 10k oh m r100 res0402 10k oh m sync r104 res0402 0ohm r46 res0402 33 oh m 200 r76 r45 res0603 57.6 oh m ld reset b sync b pd b ref_se l vs vs vs vs vcxo_clk- vcxo_clk+ vcp vcp lf cp 4 5 6 3 2 1 u25 oscvectron_vs500 c91 sel c90 sel c25 0.1u c26 0.1u 2 1 sma200up s12 1 tp1 4 5 6 3 2 1 nl27wz04 u3 bypass_ldo figure 89. evaluation board schematic, optional ad9516 loop filter/vco and sync input
ad6655 rev. 0 | page 69 of 84 06709-205 j7 - installfor pdwn j8 - installforoutputdisabl e j5 - installforiv vref/2vinputspan j4 - installfor 0.5v vref/iv inputspan j6 - installfor externalreferencemode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 u1 avdd r112 res040 2 0ohm r115 res0402 0ohm r113 res0402 0ohm 1 tp6 r63 res0402 10kohm c15 1u 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r60 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r59 fd0b 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r57 fd1b fd2b fd3b d0b d1b d2b d3b d4b d5b d13b d12b d11b d10b d9b d8b d7b d6b dco b dco a d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a d11a d12a d13a dvdd avdd pwr_sdf s fd0a pwr_sd o pwr_scl k fd3a fd2a fd1a drvdd 1 1 1 1 c109 0.1u c121 0.1u c122 0.001u c126 0.001u c127 0.001u c34 0.1u c33 0.001u c35 0.001u c36 0.1u c32 0.1u c14 0.1u c40 0.1u c120 0.1u 5 6 7 8 4 3 2 1 22ohm rpak4 r58 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r61 1 tp3 1 tp5 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 22ohm rpak8 r62 dvdd dvdd sync spi_csb clk - clk+ avdd vin+a vin-a vin-b vin+b avdd avdd spi_sdi o spi_scl k drvd d cml drvd d c137 0.001u r64 res0402 0ohm avdd1 avdd2 clk+ clk- cml d0b_lsb_ d10a d10b d11a d11b d12a d12b d13a_msb_ d13b_msb _ d1a d1b d2a d2b d3a d3b d4a d4b d5a d5b d6a d6b d7a d7b d8a d8b d9a d9b dcoa dcob doa_lsb _ drgnd drgnd1 drvdd drvdd1 dvdd1 dvdd2 fd0a fd0b fd1a fd1b fd2a fd2b fd3a fd3b avdd3 pwr_sclk_pdwn pwr_sdfs pwr_sdo/oeb rbias sense spi_csb spi_sclk/dfs spi_sdio/dcs sync vin+a vin+b vin-a vin-b vref ad6655 figure 90. evaluation board schematic, dut
ad6655 rev. 0 | page 70 of 84 06709-206 test test test test val channela channelb digital/hsc- a dc-ev a l c zinterface 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74vcx162244mtd u15 sdi csb sclk r145 res0402 0ohm r142 res0402 0ohm sdo r141 res0402 0ohm r119 res0402 0ohm csb_2 v_dig vs r140 res040 2 10kohm r118 res040 2 10kohm r130 r77 100ohm sync out6n out6p out6p out6n fd0b fd1b dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm-zd j11 v_di g v_di g fd2b fd3b d0b d1b d2b d3b v_di g d4b d5b d6b d7b v_di g v_dig v_di g v_di g d8b d9b d10b d11b d12b d13b dco b dco a d0a d1a d2a d3a d4a d5a d6a d7a d8a d9a d10a d11a v_di g d12a d13a fd3a fd2a fd1a fd0a v_di g pwr_sdo pwr_sdfs sclk_ou t sdfs_out sdo_ou t pwr_sclk sdo_ou t 1 tp23 sclk_ou t sdfs_ou t 1 tp21 v_dig c65 0.1u vs c71 0.1u c70 0.1u c69 0.1u c68 0.1u c66 0.1u c67 0.1u c72 0.1u c73 0.1u c76 0.1u c74 0.1u c75 0.1u resetb dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm-zd j12 dg10 dg9 dg8 dg7 dg6 dg5 dg4 dg3 dg2 dg1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 bg10 bg9 bg8 bg7 bg6 bg5 bg4 bg3 bg2 bg1 tyco_hm-zd j10 1 tp22 1 tp24 v_di g r143 res0402 0ohm r144 res0402 0ohm figure 91. evaluation board sche matic, digital output interface
ad6655 rev. 0 | page 71 of 84 06709-207 y1 vcc y2 a1 gnd a2 y1 vcc y2 a1 gnd a2 j1 - jumperpins 2 to 3 for spi operatio n jumperpins 1 to 2 for dcs enable j2 - jumperpins 2 to 3 for spi operatio n jumperpins 1 to 2 for twos compliment output j21 - installjumperfor spi operatio n 1 3 j2 1 3 j1 csb_2 r23 res0603 100kohm r22 res0603 100kohm r17 res0603 100kohm r65 res040 2 10kohm c81 0.1u r24 res0402 10kohm r21 res0603 1kohm r19 res0603 1kohm r18 res0402 10kohm r20 res0603 1kohm c13 0.1u s di s do s clk csb v_di g sdi vs sdo v_dig v_dig v_di g spi_sdi o spi_scl k spi_cs b v_di g v_di g v_di g sclk csb 3 2 1 4 5 6 nc7wz16p6x u8 3 2 1 4 5 6 nc7wz07p6x u7 figure 92. evaluation board schematic, spi circuitry
ad6655 rev. 0 | page 72 of 84 06709-208 1 p1 2 p2 3 p3 4 p4 5 p5 6 p6 p1 p2 p3 p4 smdc110f gnd in pad 4 out ac adp3334 3 fb gnd 5 8 in in2 7 1 out out2 2 sd 6 bias psg cb cg cg cg 6v, 2a max powe r inpu t bnx-01 6 o ptional power supply input s drvdd settin g drvd d r1 3 r1 4 3.3 1.8 2.5 140 k 107 k 76.8 k 78.7 k 94.0 k 147 k gnd test point s 1 3 2 4 5 6 f1 vr1 21 s2a_rec t cr12 21 s2a_rec t cr11 21 shot_rect cr8 21 s2a_rec t cr7 1 3 adp3339 vr3 vs drvddi n c103 0.1u sj35 avddi n c102 10u c52 10u vcp f2 pwr_i n 21 s2a_rec t cr10 c42 1u 2 3 1 power_jack j16 c53 10u c54 10u c41 10u c59 0.1u c58 0.1u c57 0.1u 1 tp4 2 1 10u h ind1210 l3 1 tp25 v_di g dvdd drvd d avd d drvddi n avddi n 1 1 c45 1u c44 1u c43 1u c93 0.001u p4 12 l6 ind1210 10u h 1 tp13 1 tp12 1 tp10 1 tp9 2 1 10u h ind1210 l11 2 1 10u h ind1210 l10 2 1 10u h ind1210 l4 2 1 10u h ind1210 l9 p3 r16 res0603 261 oh m r13 76.8 koh m r14 147k oh m figure 93. evaluation board schematic, power supply
ad6655 rev. 0 | page 73 of 84 06709-209 adp3334 fb gnd in in2 out out2 sd gnd in pad 4 out gnd in pad 4 out gnd in pad 4 out power supply bypass capaci tors 1 3 adp333 9 vr6 1 3 adp333 9 vr5 1 3 adp333 9 vr4 sj36 sj37 c124 10u c118 10u c119 10u c108 0.1u c105 0.1u c116 0.1u c107 0.1u c113 0.1u vs c114 0.1u c115 0.1u c111 0.1u c112 0.1u c110 0.1u 2 1 10uh ind1210 l12 ampvdd c129 1u vcp vcp vs vs_out_d r 3 5 8 7 1 2 6 vr2 c135 1u c136 1u c132 1u c131 1u c134 1u c133 1u c130 1u c95 0.001u 2 1 10uh ind1210 l13 2 1 10u h ind1210 l1 2 1 10u h ind1210 l8 pwr_in pwr_in pwr_in pwr_in r15 78.7koh m r25 140koh m vcp vs_out_d r vs figure 94. evaluation board schematic, power supply (continued)
ad6655 rev. 0 | page 74 of 84 evaluation board layouts 06709-100 figure 95. evaluation board layout, primary side
ad6655 rev. 0 | page 75 of 84 0 6709-101 figure 96. evaluation board layout, ground plane
ad6655 rev. 0 | page 76 of 84 0 6709-102 figure 97. evaluation board layout, power plane
ad6655 rev. 0 | page 77 of 84 0 6709-103 figure 98. evaluation board layout, power plane
ad6655 rev. 0 | page 78 of 84 06709-104 figure 99. evaluation board layout, ground plane
ad6655 rev. 0 | page 79 of 84 0 6709-105 figure 100. evaluation board layout, secondary side (mirrored image)
ad6655 rev. 0 | page 80 of 84 06709-106 figure 101. evaluation board layout, silkscreen, primary side
ad6655 rev. 0 | page 81 of 84 0 6709-107 figure 102. evaluation board layout, silkscreen, secondary side
ad6655 rev. 0 | page 82 of 84 bill of materials table 30. evaluation board bill of materials (bom) 1 , 2 item qty reference designator description package manufacturer mfg. part number 1 1 ad6655ce_revb pcb pcb analog devices 2 55 c1 to c3, c6, c7, c13, c14, c17, c18, c20 to c26, c32, c57 to c61, c65 to c76, c81 to c83, c96 to c101, c103, c105, c 107, c108, c110 to c116, c145 0.1 f, 16 v ceramic capacitor, smt 0402 c0402sm murata grm155r71c104ka88d 3 1 c80 18 pf, cog, 50 v, 5% ceramic capacitor, smt 0402 c0402sm murata gjm1555c1h180jb01j 4 2 c5, c84 4.7 pf, cog, 50 v, 5% ceramic capacitor, smt 0402 c0402sm murata gjm1555c1h4r7cb01j 5 10 c33, c35, c63, c93 to c95, c122, c126, c 127, c137 0.001 f, x7r, 25 v, 10% ceramic capacitor, smt 0402 c0402sm murata grm155r71h102ka01d 6 13 c15, c42 to c45, c129 to c136 1 f, x5r, 25 v, 10% ceramic capacitor, smt 0805 c0805 murata gr4m219r61a105kc01d 7 10 c27, c41, c52 to c54, c62, c102, c118, c119, c124 10 f, x5r, 10 v, 10% ceramic capacitor, smt 1206 c1206 murata grm31cr61c106kc31l 8 1 cr5 schottky diode hsms2822, sot23 sot23 avago technologies hsms- 2822-blkg 9 2 cr6, cr9 led red, smt, 0603, ss-type led0603 panasonic lnj208r8ara 10 4 cr7, cr10 to cr12 50 v, 2 a diode do_214aa micro commercial components s2a-tp 11 1 cr8 30 v, 3 a diode do_214ab micro commercial components sk33-tp 12 1 f1 emi filter flthmuratabnx01 murata bnx016-01 13 1 f2 6.0 v, 3.0 a, trip current resettable fuse l1206 tyco raychem nanosmdc150f-2 14 2 j1, j2 3-pin, male, single row, straight header hdr3 samtec tws-1003-08-g-s 15 9 j4 to j9, j18, j19, j21 2-pin, male, straight header hdr2 samtec tws-102-08-g-s 16 3 j10 to j12 interface connect or tyco_hm_zd tyco 6469169-1 17 1 j14 8-pin, male, double row, straight header cnberg2x4h350ld samtec tsw-104-08-t-d 18 1 j16 dc power jack connector pwr_jack1 cui stack pj-002a 19 10 l1, l3, l4, l6, l8 to l13 10 h, 2 a bead core, 1210 1210 panasonic exc-cl3225u1 20 1 p3 6-terminal connector ptmicro6 weiland electric, inc. z5.531.3625.0 21 1 p4 4-terminal connector ptmicro4 weiland electric, inc. z5.531.3425.0 22 3 r7, r30, r45 57.6 , 0603, 1/10 w, 1% resistor r0603 nic components nrc06f57r6trf 23 27 r2, r3, r4, r32, r33, r42, r64, r67, r69, r90, r96, r99, r101, r104, r110 to f113, r115, r119, r 121, r123, r141 to r145 0 , 1/16 w, 5% resistor r0402sm nic components nrc04zotrf 24 1 r13 76.8 k, 0603, 1/10 w, 1% resistor r 0603 nic components nrc06f 7682trf 25 1 r25 140 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f1403trf 26 1 r14 147 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f1473trf 27 1 r15 78.7 k, 0603, 1/10 w, 1% resistor r 0603 nic components nrc06f 7872trf
ad6655 rev. 0 | page 83 of 84 item qty reference designator description package manufacturer mfg. part number 28 1 r16 261 , 0603, 1/10 w, 1% resistor r 0603 nic components nrc06f 2610trf 29 3 r17, r22, r23 100 k, 0603, 1/10 w, 1% resistor r 0603 nic components nrc06f 1003trf 30 7 r18, r24, r63, r65, r82, r118, r140 10 k, 0402, 1/16 w, 1% resistor r0402sm nic components nrc04f 1002trf 31 3 r19, r21 1 k, 0603, 1/10 w, 1% resistor r0603 nic components nrc06f 1001trf 32 9 r26, r27, r43, r46, r47, r70, r71, r73, r74 33 , 0402, 1/16 w, 5% resistor r0402sm nic components nrc04j330trf 33 5 r57, r59 to r62 22 , 16-pin, 8-resistor, resistor array r_742 cts corporation 742c163220jptr 34 1 r58 22 , 8-pin, 4-resistor, resistor array res_arry cts corporation 742c083220jptr 35 1 r76 200 , 0402, 1/16 w, 1% resistor r0402sm nic components ncr04f 2000trf 36 4 s2, s3, s5, s12 sma, inline, male, coaxial connector sma_edge emerson network power 142-0701-201 37 1 sj35 0 , 1/8 w, 1% resistor sldr_pad2muylar nic components nrc10zotrf 38 5 t1 to t5 balun tran6b m/a-com maba-007159-000000 39 1 u1 ic, ad6655 lfcsp64-9x9-9e analog devices ad6655bcpz 40 1 u2 clock distribution, pll ic lfc sp64-9x9 analog devices ad9516-4bcpz 41 1 u3 dual inverter ic sc70_6 fairchild semiconductor nc7wz04p6x_nl 42 1 u7 dual buffer ic, open-drain circuits sc70_6 fairchild semiconductor nc7wz07p6x_nl 43 1 u8 uhs dual buffer ic sc70_6 fairchild semiconductor nc7wz16p6x_nl 44 3 u15 to u17 16-bit cmos buffer ic tsop48_8_ 1mm fairchild semiconductor 74vcx16244mtdx_nl 45 2 vr1, vr2 adjustable regulator lfc sp8-3x3 analog devices adp3334acpz 46 1 vr3 1.8 v high accuracy regulator so t223-hs analog devices adp3339akcz-1.8 47 1 vr4 5.0 v high accuracy regulator so t223-hs analog devices adp3339akcz-5.0 48 2 vr5, vr6 3.3 v high accuracy regulato r sot223-hs analog de vices adp3339akcz-3.3 49 1 y1 oscillator clock, vfac3 osc- cts-cb3 valpey fisher vfac3-bhl 50 2 z1, z2 high speed ic, op amp lfcsp16-3x3-pad analog devices ad8352acpz 1 this bill of materials is rohs compliant. 2 the bill of materials lists only those items that are normally installed in the default condition. items that are not installe d are not included in the bom.
ad6655 rev. 0 | page 84 of 84 outline dimensions compliant to jedec standards mo-220-vmmd-4 051007-c 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator 7.25 7.10 sq 6.95 pin 1 indicator 0.30 0.23 0.18 figure 103. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-3) dimensions shown in millimeters ordering guide model temperature range package description package option ad6655bcpz-150 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 ad6655bcpz-125 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 ad6655bcpz-105 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 ad6655bcpz-80 1 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-3 ad6655-125ebz 1 evaluation board with ad6655 and software ad6655-150ebz 1 evaluation board with ad6655 and software 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06709-0-11/07(0)

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